Lines Matching +full:rockchip +full:- +full:display
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 compatible = "rockchip,rk3036";
17 interrupt-parent = <&gic>;
36 #address-cells = <1>;
37 #size-cells = <0>;
38 enable-method = "rockchip,rk3036-smp";
42 compatible = "arm,cortex-a7";
45 operating-points = <
49 clock-latency = <40000>;
55 compatible = "arm,cortex-a7";
61 arm-pmu {
62 compatible = "arm,cortex-a7-pmu";
65 interrupt-affinity = <&cpu0>, <&cpu1>;
68 display-subsystem {
69 compatible = "rockchip,display-subsystem";
74 compatible = "arm,armv7-timer";
75 arm,cpu-registers-not-fw-configured;
80 clock-frequency = <24000000>;
84 compatible = "fixed-clock";
85 clock-frequency = <24000000>;
86 clock-output-names = "xin24m";
87 #clock-cells = <0>;
91 compatible = "mmio-sram";
93 #address-cells = <1>;
94 #size-cells = <1>;
97 smp-sram@0 {
98 compatible = "rockchip,rk3066-smp-sram";
104 compatible = "rockchip,rk3036-mali", "arm,mali-400";
110 interrupt-names = "gp",
114 assigned-clocks = <&cru SCLK_GPU>;
115 assigned-clock-rates = <100000000>;
117 clock-names = "bus", "core";
118 power-domains = <&power RK3036_PD_GPU>;
123 vpu: video-codec@10108000 {
124 compatible = "rockchip,rk3036-vpu";
127 interrupt-names = "vdpu";
129 clock-names = "aclk", "hclk";
131 power-domains = <&power RK3036_PD_VPU>;
135 compatible = "rockchip,iommu";
139 clock-names = "aclk", "iface";
140 power-domains = <&power RK3036_PD_VPU>;
141 #iommu-cells = <0>;
145 compatible = "rockchip,rk3036-vop";
149 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
151 reset-names = "axi", "ahb", "dclk";
153 power-domains = <&power RK3036_PD_VIO>;
157 #address-cells = <1>;
158 #size-cells = <0>;
161 remote-endpoint = <&hdmi_in_vop>;
167 compatible = "rockchip,iommu";
171 clock-names = "aclk", "iface";
172 power-domains = <&power RK3036_PD_VIO>;
173 #iommu-cells = <0>;
178 compatible = "rockchip,rk3036-qos", "syscon";
183 compatible = "rockchip,rk3036-qos", "syscon";
188 compatible = "rockchip,rk3036-qos", "syscon";
192 gic: interrupt-controller@10139000 {
193 compatible = "arm,gic-400";
194 interrupt-controller;
195 #interrupt-cells = <3>;
196 #address-cells = <0>;
206 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
211 clock-names = "otg";
213 g-np-tx-fifo-size = <16>;
214 g-rx-fifo-size = <275>;
215 g-tx-fifo-size = <256 128 128 64 64 32>;
217 phy-names = "usb2-phy";
222 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
227 clock-names = "otg";
230 phy-names = "usb2-phy";
235 compatible = "rockchip,rk3036-emac";
238 rockchip,grf = <&grf>;
240 clock-names = "hclk", "macref", "macclk";
246 assigned-clocks = <&cru SCLK_MACPLL>;
247 assigned-clock-parents = <&cru PLL_DPLL>;
248 max-speed = <100>;
249 phy-mode = "rmii";
254 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
256 clock-frequency = <37500000>;
257 max-frequency = <37500000>;
259 clock-names = "biu", "ciu";
260 fifo-depth = <0x100>;
263 reset-names = "reset";
268 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
270 max-frequency = <37500000>;
273 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
274 fifo-depth = <0x100>;
277 reset-names = "reset";
282 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
285 bus-width = <8>;
286 cap-mmc-highspeed;
287 clock-frequency = <37500000>;
288 max-frequency = <37500000>;
291 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
292 disable-wp;
294 dma-names = "rx-tx";
295 fifo-depth = <0x100>;
296 mmc-ddr-1_8v;
297 non-removable;
298 pinctrl-names = "default";
299 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
301 reset-names = "reset";
306 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
309 clock-names = "i2s_clk", "i2s_hclk";
312 dma-names = "tx", "rx";
313 pinctrl-names = "default";
314 pinctrl-0 = <&i2s_bus>;
315 #sound-dai-cells = <0>;
319 nfc: nand-controller@10500000 {
320 compatible = "rockchip,rk3036-nfc",
321 "rockchip,rk2928-nfc";
325 clock-names = "ahb", "nfc";
326 assigned-clocks = <&cru SCLK_NANDC>;
327 assigned-clock-rates = <150000000>;
328 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
330 pinctrl-names = "default";
334 cru: clock-controller@20000000 {
335 compatible = "rockchip,rk3036-cru";
338 clock-names = "xin24m";
339 rockchip,grf = <&grf>;
340 #clock-cells = <1>;
341 #reset-cells = <1>;
342 assigned-clocks = <&cru PLL_GPLL>;
343 assigned-clock-rates = <594000000>;
347 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
349 #address-cells = <1>;
350 #size-cells = <1>;
353 compatible = "rockchip,rk3036-usb2phy";
356 clock-names = "phyclk";
357 clock-output-names = "usb480m_phy";
358 assigned-clocks = <&cru SCLK_USB480M>;
359 assigned-clock-parents = <&usb2phy>;
360 #clock-cells = <0>;
363 usb2phy_host: host-port {
365 interrupt-names = "linestate";
366 #phy-cells = <0>;
370 usb2phy_otg: otg-port {
374 interrupt-names = "otg-bvalid", "otg-id",
376 #phy-cells = <0>;
381 power: power-controller {
382 compatible = "rockchip,rk3036-power-controller";
383 #power-domain-cells = <1>;
384 #address-cells = <1>;
385 #size-cells = <0>;
387 power-domain@RK3036_PD_VIO {
393 #power-domain-cells = <0>;
396 power-domain@RK3036_PD_VPU {
401 #power-domain-cells = <0>;
404 power-domain@RK3036_PD_GPU {
408 #power-domain-cells = <0>;
412 reboot-mode {
413 compatible = "syscon-reboot-mode";
415 mode-normal = <BOOT_NORMAL>;
416 mode-recovery = <BOOT_RECOVERY>;
417 mode-bootloader = <BOOT_FASTBOOT>;
418 mode-loader = <BOOT_BL_DOWNLOAD>;
422 acodec: audio-codec@20030000 {
423 compatible = "rockchip,rk3036-codec";
425 clock-names = "acodec_pclk";
427 rockchip,grf = <&grf>;
428 #sound-dai-cells = <0>;
433 compatible = "rockchip,rk3036-inno-hdmi";
437 clock-names = "pclk", "ref";
438 rockchip,grf = <&grf>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&hdmi_ctl>;
441 #sound-dai-cells = <0>;
445 #address-cells = <1>;
446 #size-cells = <0>;
452 remote-endpoint = <&vop_out_hdmi>;
463 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
467 clock-names = "pclk", "timer";
471 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
473 #pwm-cells = <3>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&pwm0_pin>;
481 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
483 #pwm-cells = <3>;
485 pinctrl-names = "default";
486 pinctrl-0 = <&pwm1_pin>;
491 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
493 #pwm-cells = <3>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&pwm2_pin>;
501 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
503 #pwm-cells = <2>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&pwm3_pin>;
511 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
514 #address-cells = <1>;
515 #size-cells = <0>;
516 clock-names = "i2c";
518 pinctrl-names = "default";
519 pinctrl-0 = <&i2c1_xfer>;
524 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
527 #address-cells = <1>;
528 #size-cells = <0>;
529 clock-names = "i2c";
531 pinctrl-names = "default";
532 pinctrl-0 = <&i2c2_xfer>;
537 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
540 reg-shift = <2>;
541 reg-io-width = <4>;
542 clock-frequency = <24000000>;
544 clock-names = "baudclk", "apb_pclk";
545 pinctrl-names = "default";
546 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
551 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
554 reg-shift = <2>;
555 reg-io-width = <4>;
556 clock-frequency = <24000000>;
558 clock-names = "baudclk", "apb_pclk";
559 pinctrl-names = "default";
560 pinctrl-0 = <&uart1_xfer>;
565 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
568 reg-shift = <2>;
569 reg-io-width = <4>;
570 clock-frequency = <24000000>;
572 clock-names = "baudclk", "apb_pclk";
573 pinctrl-names = "default";
574 pinctrl-0 = <&uart2_xfer>;
579 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
582 #address-cells = <1>;
583 #size-cells = <0>;
584 clock-names = "i2c";
586 pinctrl-names = "default";
587 pinctrl-0 = <&i2c0_xfer>;
592 compatible = "rockchip,rk3036-spi";
596 clock-names = "spiclk", "apb_pclk";
598 dma-names = "tx", "rx";
599 pinctrl-names = "default";
600 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
601 #address-cells = <1>;
602 #size-cells = <0>;
606 pdma: dma-controller@20078000 {
611 #dma-cells = <1>;
612 arm,pl330-broken-no-flushp;
613 arm,pl330-periph-burst;
615 clock-names = "apb_pclk";
619 compatible = "rockchip,rk3036-pinctrl";
620 rockchip,grf = <&grf>;
621 #address-cells = <1>;
622 #size-cells = <1>;
626 compatible = "rockchip,gpio-bank";
631 gpio-controller;
632 #gpio-cells = <2>;
634 interrupt-controller;
635 #interrupt-cells = <2>;
639 compatible = "rockchip,gpio-bank";
644 gpio-controller;
645 #gpio-cells = <2>;
647 interrupt-controller;
648 #interrupt-cells = <2>;
652 compatible = "rockchip,gpio-bank";
657 gpio-controller;
658 #gpio-cells = <2>;
660 interrupt-controller;
661 #interrupt-cells = <2>;
664 pcfg_pull_default: pcfg-pull-default {
665 bias-pull-pin-default;
668 pcfg_pull_none: pcfg-pull-none {
669 bias-disable;
673 pwm0_pin: pwm0-pin {
674 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
679 pwm1_pin: pwm1-pin {
680 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
685 pwm2_pin: pwm2-pin {
686 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
691 pwm3_pin: pwm3-pin {
692 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
697 sdmmc_clk: sdmmc-clk {
698 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
701 sdmmc_cmd: sdmmc-cmd {
702 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
705 sdmmc_cd: sdmmc-cd {
706 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
709 sdmmc_bus1: sdmmc-bus1 {
710 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
713 sdmmc_bus4: sdmmc-bus4 {
714 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
722 sdio_bus1: sdio-bus1 {
723 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
726 sdio_bus4: sdio-bus4 {
727 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
733 sdio_cmd: sdio-cmd {
734 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
737 sdio_clk: sdio-clk {
738 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
747 emmc_clk: emmc-clk {
748 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
751 emmc_cmd: emmc-cmd {
752 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
755 emmc_bus8: emmc-bus8 {
756 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
768 flash_ale: flash-ale {
769 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;
772 flash_bus8: flash-bus8 {
773 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,
783 flash_cle: flash-cle {
784 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;
787 flash_csn0: flash-csn0 {
788 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;
791 flash_rdn: flash-rdn {
792 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;
795 flash_rdy: flash-rdy {
796 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;
799 flash_wrn: flash-wrn {
800 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;
805 emac_xfer: emac-xfer {
806 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
816 emac_mdio: emac-mdio {
817 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
823 i2c0_xfer: i2c0-xfer {
824 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
830 i2c1_xfer: i2c1-xfer {
831 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
837 i2c2_xfer: i2c2-xfer {
838 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
844 i2s_bus: i2s-bus {
845 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
855 hdmi_ctl: hdmi-ctl {
856 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
864 uart0_xfer: uart0-xfer {
865 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
869 uart0_cts: uart0-cts {
870 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
873 uart0_rts: uart0-rts {
874 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
879 uart1_xfer: uart1-xfer {
880 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
887 uart2_xfer: uart2-xfer {
888 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
894 spi-pins {
895 spi_txd:spi-txd {
896 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
899 spi_rxd:spi-rxd {
900 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
903 spi_clk:spi-clk {
904 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
907 spi_cs0:spi-cs0 {
908 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
912 spi_cs1:spi-cs1 {
913 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;