Lines Matching refs:sysctrl

10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
25 			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
32 			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
76 			clocks = <&sysctrl R9A06G032_HCLK_RTC>, <&ext_rtc_clk>;
78 			power-domains = <&sysctrl>;
86 			clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
94 			clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
98 		sysctrl: system-controller@4000c000 {  label
99 			compatible = "renesas,r9a06g032-sysctrl";
125 			clocks = <&sysctrl R9A06G032_HCLK_USBF>,
126 				 <&sysctrl R9A06G032_HCLK_USBPM>;
128 			power-domains = <&sysctrl>;
135 			clocks = <&sysctrl R9A06G032_HCLK_USBH>,
136 				 <&sysctrl R9A06G032_HCLK_USBPM>,
137 				 <&sysctrl R9A06G032_CLK_PCI_USB>;
139 			power-domains = <&sysctrl>;
179 			clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
190 			clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
201 			clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
212 			clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
225 			clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
238 			clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
251 			clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
264 			clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
275 			clocks = <&sysctrl R9A06G032_HCLK_I2C0>, <&sysctrl R9A06G032_CLK_I2C0>;
286 			clocks = <&sysctrl R9A06G032_HCLK_I2C1>, <&sysctrl R9A06G032_CLK_I2C1>;
296 			clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
307 			clocks = <&sysctrl R9A06G032_CLK_SDIO0>, <&sysctrl R9A06G032_HCLK_SDIO0>;
319 			clocks = <&sysctrl R9A06G032_CLK_SDIO1>, <&sysctrl R9A06G032_HCLK_SDIO1>;
329 			clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
331 			power-domains = <&sysctrl>;
342 			clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
356 			clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
372 			clocks = <&sysctrl R9A06G032_HCLK_GMAC0>;
374 			power-domains = <&sysctrl>;
390 			clocks = <&sysctrl R9A06G032_HCLK_GMAC1>;
392 			power-domains = <&sysctrl>;
405 			clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
406 				 <&sysctrl R9A06G032_CLK_RGMII_REF>,
407 				 <&sysctrl R9A06G032_CLK_RMII_REF>,
408 				 <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
410 			power-domains = <&sysctrl>;
442 			clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
443 				 <&sysctrl R9A06G032_CLK_SWITCH>;
445 			power-domains = <&sysctrl>;
507 			clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
508 			power-domains = <&sysctrl>;
517 			clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
518 			power-domains = <&sysctrl>;