Lines Matching +full:0 +full:xe6520000
34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
66 cpu0: cpu@0 {
69 reg = <0>;
88 L2_CA7: cache-controller-0 {
99 #clock-cells = <0>;
101 clock-frequency = <0>;
114 #clock-cells = <0>;
116 clock-frequency = <0>;
130 reg = <0 0xe6020000 0 0x0c>;
141 reg = <0 0xe6050000 0 0x50>;
145 gpio-ranges = <&pfc 0 0 32>;
156 reg = <0 0xe6051000 0 0x50>;
160 gpio-ranges = <&pfc 0 32 26>;
171 reg = <0 0xe6052000 0 0x50>;
175 gpio-ranges = <&pfc 0 64 32>;
186 reg = <0 0xe6053000 0 0x50>;
190 gpio-ranges = <&pfc 0 96 32>;
201 reg = <0 0xe6054000 0 0x50>;
205 gpio-ranges = <&pfc 0 128 32>;
216 reg = <0 0xe6055000 0 0x50>;
220 gpio-ranges = <&pfc 0 160 28>;
231 reg = <0 0xe6055400 0 0x50>;
235 gpio-ranges = <&pfc 0 192 26>;
245 reg = <0 0xe6060000 0 0x11c>;
250 reg = <0 0xe6150000 0 0x1000>;
254 #power-domain-cells = <0>;
260 reg = <0 0xe6151000 0 0x188>;
266 reg = <0 0xe6160000 0 0x0100>;
271 reg = <0 0xe6180000 0 0x0200>;
279 reg = <0 0xe61c0000 0 0x200>;
280 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
297 reg = <0 0xe61e0000 0 0x30>;
311 reg = <0 0xfff60000 0 0x30>;
326 reg = <0 0xfff70000 0 0x30>;
341 reg = <0 0xfff80000 0 0x30>;
356 reg = <0 0xe6280000 0 0x1000>;
366 reg = <0 0xe6290000 0 0x1000>;
375 reg = <0 0xe6740000 0 0x1000>;
385 reg = <0 0xec680000 0 0x1000>;
394 reg = <0 0xfe951000 0 0x1000>;
404 reg = <0 0xe62a0000 0 0x1000>;
413 reg = <0 0xe63a0000 0 0x12000>;
416 ranges = <0 0 0xe63a0000 0x12000>;
421 reg = <0 0xe63c0000 0 0x1000>;
424 ranges = <0 0 0xe63c0000 0x1000>;
426 smp-sram@0 {
428 reg = <0 0x100>;
438 reg = <0 0xe6508000 0 0x40>;
444 #size-cells = <0>;
452 reg = <0 0xe6518000 0 0x40>;
458 #size-cells = <0>;
466 reg = <0 0xe6530000 0 0x40>;
472 #size-cells = <0>;
480 reg = <0 0xe6540000 0 0x40>;
486 #size-cells = <0>;
494 reg = <0 0xe6520000 0 0x40>;
500 #size-cells = <0>;
508 reg = <0 0xe6528000 0 0x40>;
514 #size-cells = <0>;
523 reg = <0 0xe6500000 0 0x425>;
526 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
527 <&dmac1 0x61>, <&dmac1 0x62>;
532 #size-cells = <0>;
540 reg = <0 0xe6510000 0 0x425>;
543 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
544 <&dmac1 0x65>, <&dmac1 0x66>;
549 #size-cells = <0>;
556 reg = <0 0xe6590000 0 0x100>;
570 reg = <0 0xe6590100 0 0x100>;
572 #size-cells = <0>;
579 usb0: usb-phy@0 {
580 reg = <0>;
592 reg = <0 0xe6700000 0 0x20000>;
625 reg = <0 0xe6720000 0 0x20000>;
658 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
665 #size-cells = <0>;
671 reg = <0 0xe6b10000 0 0x2c>;
674 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
675 <&dmac1 0x17>, <&dmac1 0x18>;
681 #size-cells = <0>;
688 reg = <0 0xe6c40000 0 64>;
692 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
693 <&dmac1 0x21>, <&dmac1 0x22>;
703 reg = <0 0xe6c50000 0 64>;
707 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
708 <&dmac1 0x25>, <&dmac1 0x26>;
718 reg = <0 0xe6c60000 0 64>;
722 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
723 <&dmac1 0x27>, <&dmac1 0x28>;
733 reg = <0 0xe6c70000 0 64>;
737 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
738 <&dmac1 0x1b>, <&dmac1 0x1c>;
748 reg = <0 0xe6c78000 0 64>;
752 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
753 <&dmac1 0x1f>, <&dmac1 0x20>;
763 reg = <0 0xe6c80000 0 64>;
767 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
768 <&dmac1 0x23>, <&dmac1 0x24>;
778 reg = <0 0xe6c20000 0 0x100>;
782 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
783 <&dmac1 0x3d>, <&dmac1 0x3e>;
793 reg = <0 0xe6c30000 0 0x100>;
797 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
798 <&dmac1 0x19>, <&dmac1 0x1a>;
808 reg = <0 0xe6ce0000 0 0x100>;
812 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
813 <&dmac1 0x1d>, <&dmac1 0x1e>;
824 reg = <0 0xe6e60000 0 64>;
829 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
830 <&dmac1 0x29>, <&dmac1 0x2a>;
841 reg = <0 0xe6e68000 0 64>;
846 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
847 <&dmac1 0x2d>, <&dmac1 0x2e>;
857 reg = <0 0xe6e58000 0 64>;
862 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
863 <&dmac1 0x2b>, <&dmac1 0x2c>;
873 reg = <0 0xe6ea8000 0 64>;
878 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
879 <&dmac1 0x2f>, <&dmac1 0x30>;
889 reg = <0 0xe6ee0000 0 64>;
894 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
895 <&dmac1 0xfb>, <&dmac1 0xfc>;
905 reg = <0 0xe6ee8000 0 64>;
910 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
911 <&dmac1 0xfd>, <&dmac1 0xfe>;
921 reg = <0 0xe62c0000 0 96>;
926 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
927 <&dmac1 0x39>, <&dmac1 0x3a>;
937 reg = <0 0xe62c8000 0 96>;
942 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
943 <&dmac1 0x4d>, <&dmac1 0x4e>;
953 reg = <0 0xe62d0000 0 96>;
958 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
959 <&dmac1 0x3b>, <&dmac1 0x3c>;
969 reg = <0 0xe6e80000 0 0x1000>;
982 reg = <0 0xe6e88000 0 0x1000>;
995 reg = <0 0xe6ef0000 0 0x1000>;
1006 reg = <0 0xe6ef1000 0 0x1000>;
1018 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1023 reg = <0 0xec500000 0 0x1000>, /* SCU */
1024 <0 0xec5a0000 0 0x100>, /* ADG */
1025 <0 0xec540000 0 0x1000>, /* SSIU */
1026 <0 0xec541000 0 0x280>, /* SSI */
1027 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
1047 "ssi.1", "ssi.0",
1050 "ctu.0", "ctu.1",
1051 "mix.0", "mix.1",
1052 "dvc.0", "dvc.1",
1064 "ssi.1", "ssi.0";
1069 dvc0: dvc-0 {
1070 dmas = <&audma0 0xbc>;
1074 dmas = <&audma0 0xbe>;
1080 mix0: mix-0 { };
1085 ctu00: ctu-0 { };
1096 src-0 {
1101 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1106 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1111 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1116 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1121 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1126 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1132 ssi0: ssi-0 {
1134 dmas = <&audma0 0x01>, <&audma0 0x02>,
1135 <&audma0 0x15>, <&audma0 0x16>;
1140 dmas = <&audma0 0x03>, <&audma0 0x04>,
1141 <&audma0 0x49>, <&audma0 0x4a>;
1146 dmas = <&audma0 0x05>, <&audma0 0x06>,
1147 <&audma0 0x63>, <&audma0 0x64>;
1152 dmas = <&audma0 0x07>, <&audma0 0x08>,
1153 <&audma0 0x6f>, <&audma0 0x70>;
1158 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1159 <&audma0 0x71>, <&audma0 0x72>;
1164 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1165 <&audma0 0x73>, <&audma0 0x74>;
1170 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1171 <&audma0 0x75>, <&audma0 0x76>;
1176 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1177 <&audma0 0x79>, <&audma0 0x7a>;
1182 dmas = <&audma0 0x11>, <&audma0 0x12>,
1183 <&audma0 0x7b>, <&audma0 0x7c>;
1188 dmas = <&audma0 0x13>, <&audma0 0x14>,
1189 <&audma0 0x7d>, <&audma0 0x7e>;
1198 reg = <0 0xec700000 0 0x10000>;
1230 reg = <0 0xee090000 0 0xc00>,
1231 <0 0xee080000 0 0x1100>;
1238 bus-range = <0 0>;
1242 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1243 interrupt-map-mask = <0xf800 0 0 0x7>;
1244 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1245 <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1246 <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1248 usb@1,0 {
1249 reg = <0x800 0 0 0 0>;
1250 phys = <&usb0 0>;
1254 usb@2,0 {
1255 reg = <0x1000 0 0 0 0>;
1256 phys = <&usb0 0>;
1265 reg = <0 0xee0d0000 0 0xc00>,
1266 <0 0xee0c0000 0 0x1100>;
1277 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1278 interrupt-map-mask = <0xf800 0 0 0x7>;
1279 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1280 <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1281 <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1283 usb@1,0 {
1284 reg = <0x10800 0 0 0 0>;
1285 phys = <&usb2 0>;
1289 usb@2,0 {
1290 reg = <0x11000 0 0 0 0>;
1291 phys = <&usb2 0>;
1299 reg = <0 0xee100000 0 0x328>;
1302 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
1303 <&dmac1 0xcd>, <&dmac1 0xce>;
1314 reg = <0 0xee140000 0 0x100>;
1317 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
1318 <&dmac1 0xc1>, <&dmac1 0xc2>;
1329 reg = <0 0xee160000 0 0x100>;
1332 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
1333 <&dmac1 0xd3>, <&dmac1 0xd4>;
1344 reg = <0 0xee200000 0 0x80>;
1347 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
1348 <&dmac1 0xd1>, <&dmac1 0xd2>;
1359 reg = <0 0xee700000 0 0x400>;
1366 #size-cells = <0>;
1373 #address-cells = <0>;
1375 reg = <0 0xf1001000 0 0x1000>,
1376 <0 0xf1002000 0 0x2000>,
1377 <0 0xf1004000 0 0x2000>,
1378 <0 0xf1006000 0 0x2000>;
1388 reg = <0 0xfe928000 0 0x8000>;
1397 reg = <0 0xfe930000 0 0x8000>;
1406 reg = <0 0xfe940000 0 0x2400>;
1415 reg = <0 0xfeb00000 0 0x40000>;
1419 clock-names = "du.0", "du.1";
1421 reset-names = "du.0";
1426 #size-cells = <0>;
1428 port@0 {
1429 reg = <0>;
1443 reg = <0 0xff000044 0 4>;
1449 reg = <0 0xffca0000 0 0x1004>;
1463 reg = <0 0xe6130000 0 0x1004>;
1493 #clock-cells = <0>;