Lines Matching +full:0 +full:xe6530000
32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
64 cpu0: cpu@0 {
67 reg = <0>;
106 L2_CA15: cache-controller-0 {
117 #clock-cells = <0>;
119 clock-frequency = <0>;
132 #clock-cells = <0>;
134 clock-frequency = <0>;
148 reg = <0 0xe6020000 0 0x0c>;
159 reg = <0 0xe6050000 0 0x50>;
163 gpio-ranges = <&pfc 0 0 32>;
174 reg = <0 0xe6051000 0 0x50>;
178 gpio-ranges = <&pfc 0 32 26>;
189 reg = <0 0xe6052000 0 0x50>;
193 gpio-ranges = <&pfc 0 64 32>;
204 reg = <0 0xe6053000 0 0x50>;
208 gpio-ranges = <&pfc 0 96 32>;
219 reg = <0 0xe6054000 0 0x50>;
223 gpio-ranges = <&pfc 0 128 32>;
234 reg = <0 0xe6055000 0 0x50>;
238 gpio-ranges = <&pfc 0 160 32>;
249 reg = <0 0xe6055400 0 0x50>;
253 gpio-ranges = <&pfc 0 192 32>;
264 reg = <0 0xe6055800 0 0x50>;
268 gpio-ranges = <&pfc 0 224 26>;
278 reg = <0 0xe6060000 0 0x250>;
284 reg = <0 0xe6150000 0 0x1000>;
288 #power-domain-cells = <0>;
294 reg = <0 0xe6152000 0 0x188>;
300 reg = <0 0xe6160000 0 0x0100>;
305 reg = <0 0xe6180000 0 0x0200>;
313 reg = <0 0xe61c0000 0 0x200>;
314 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
331 reg = <0 0xe61e0000 0 0x30>;
345 reg = <0 0xfff60000 0 0x30>;
360 reg = <0 0xfff70000 0 0x30>;
375 reg = <0 0xfff80000 0 0x30>;
391 reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
396 #thermal-sensor-cells = <0>;
402 reg = <0 0xe6280000 0 0x1000>;
412 reg = <0 0xe6290000 0 0x1000>;
421 reg = <0 0xe6740000 0 0x1000>;
431 reg = <0 0xec680000 0 0x1000>;
440 reg = <0 0xfe951000 0 0x1000>;
450 reg = <0 0xffc80000 0 0x1000>;
459 reg = <0 0xe62a0000 0 0x1000>;
468 reg = <0 0xe63a0000 0 0x12000>;
471 ranges = <0 0 0xe63a0000 0x12000>;
476 reg = <0 0xe63c0000 0 0x1000>;
479 ranges = <0 0 0xe63c0000 0x1000>;
481 smp-sram@0 {
483 reg = <0 0x100>;
492 #size-cells = <0>;
495 reg = <0 0xe6508000 0 0x40>;
506 #size-cells = <0>;
509 reg = <0 0xe6518000 0 0x40>;
520 #size-cells = <0>;
523 reg = <0 0xe6530000 0 0x40>;
534 #size-cells = <0>;
537 reg = <0 0xe6540000 0 0x40>;
548 #size-cells = <0>;
551 reg = <0 0xe6520000 0 0x40>;
563 #size-cells = <0>;
566 reg = <0 0xe6528000 0 0x40>;
578 #size-cells = <0>;
582 reg = <0 0xe60b0000 0 0x425>;
585 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
586 <&dmac1 0x77>, <&dmac1 0x78>;
595 #size-cells = <0>;
599 reg = <0 0xe6500000 0 0x425>;
602 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
603 <&dmac1 0x61>, <&dmac1 0x62>;
612 #size-cells = <0>;
616 reg = <0 0xe6510000 0 0x425>;
619 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
620 <&dmac1 0x65>, <&dmac1 0x66>;
630 reg = <0 0xe6700000 0 0x20000>;
663 reg = <0 0xe6720000 0 0x20000>;
695 reg = <0 0xe6b10000 0 0x2c>;
698 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
699 <&dmac1 0x17>, <&dmac1 0x18>;
705 #size-cells = <0>;
712 reg = <0 0xe6c40000 0 64>;
716 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
717 <&dmac1 0x21>, <&dmac1 0x22>;
727 reg = <0 0xe6c50000 0 64>;
731 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
732 <&dmac1 0x25>, <&dmac1 0x26>;
742 reg = <0 0xe6c60000 0 64>;
746 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
747 <&dmac1 0x27>, <&dmac1 0x28>;
757 reg = <0 0xe6c70000 0 64>;
761 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
762 <&dmac1 0x1b>, <&dmac1 0x1c>;
772 reg = <0 0xe6c78000 0 64>;
776 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
777 <&dmac1 0x1f>, <&dmac1 0x20>;
787 reg = <0 0xe6c80000 0 64>;
791 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
792 <&dmac1 0x23>, <&dmac1 0x24>;
802 reg = <0 0xe6c20000 0 0x100>;
806 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
807 <&dmac1 0x3d>, <&dmac1 0x3e>;
817 reg = <0 0xe6c30000 0 0x100>;
821 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
822 <&dmac1 0x19>, <&dmac1 0x1a>;
832 reg = <0 0xe6ce0000 0 0x100>;
836 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
837 <&dmac1 0x1d>, <&dmac1 0x1e>;
847 reg = <0 0xe6e60000 0 64>;
852 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
853 <&dmac1 0x29>, <&dmac1 0x2a>;
863 reg = <0 0xe6e68000 0 64>;
868 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
869 <&dmac1 0x2d>, <&dmac1 0x2e>;
879 reg = <0 0xe6e58000 0 64>;
884 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
885 <&dmac1 0x2b>, <&dmac1 0x2c>;
895 reg = <0 0xe6ea8000 0 64>;
900 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
901 <&dmac1 0x2f>, <&dmac1 0x30>;
911 reg = <0 0xe6ee0000 0 64>;
916 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
917 <&dmac1 0xfb>, <&dmac1 0xfc>;
927 reg = <0 0xe6ee8000 0 64>;
932 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
933 <&dmac1 0xfd>, <&dmac1 0xfe>;
943 reg = <0 0xe62c0000 0 96>;
948 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
949 <&dmac1 0x39>, <&dmac1 0x3a>;
959 reg = <0 0xe62c8000 0 96>;
964 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
965 <&dmac1 0x4d>, <&dmac1 0x4e>;
975 reg = <0 0xe62d0000 0 96>;
980 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
981 <&dmac1 0x3b>, <&dmac1 0x3c>;
991 reg = <0 0xe6e80000 0 0x1000>;
1004 reg = <0 0xe6e88000 0 0x1000>;
1017 reg = <0 0xe6ef0000 0 0x1000>;
1028 reg = <0 0xe6ef1000 0 0x1000>;
1039 reg = <0 0xe6ef2000 0 0x1000>;
1051 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1056 reg = <0 0xec500000 0 0x1000>, /* SCU */
1057 <0 0xec5a0000 0 0x100>, /* ADG */
1058 <0 0xec540000 0 0x1000>, /* SSIU */
1059 <0 0xec541000 0 0x280>, /* SSI */
1060 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1080 "ssi.1", "ssi.0",
1083 "src.1", "src.0",
1084 "dvc.0", "dvc.1",
1096 "ssi.1", "ssi.0";
1101 dvc0: dvc-0 {
1102 dmas = <&audma1 0xbc>;
1106 dmas = <&audma1 0xbe>;
1112 src0: src-0 {
1114 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1119 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1124 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1129 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1134 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1139 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1144 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1149 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1154 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1159 dmas = <&audma0 0x97>, <&audma1 0xba>;
1165 ssi0: ssi-0 {
1167 dmas = <&audma0 0x01>, <&audma1 0x02>,
1168 <&audma0 0x15>, <&audma1 0x16>;
1173 dmas = <&audma0 0x03>, <&audma1 0x04>,
1174 <&audma0 0x49>, <&audma1 0x4a>;
1179 dmas = <&audma0 0x05>, <&audma1 0x06>,
1180 <&audma0 0x63>, <&audma1 0x64>;
1185 dmas = <&audma0 0x07>, <&audma1 0x08>,
1186 <&audma0 0x6f>, <&audma1 0x70>;
1191 dmas = <&audma0 0x09>, <&audma1 0x0a>,
1192 <&audma0 0x71>, <&audma1 0x72>;
1197 dmas = <&audma0 0x0b>, <&audma1 0x0c>,
1198 <&audma0 0x73>, <&audma1 0x74>;
1203 dmas = <&audma0 0x0d>, <&audma1 0x0e>,
1204 <&audma0 0x75>, <&audma1 0x76>;
1209 dmas = <&audma0 0x0f>, <&audma1 0x10>,
1210 <&audma0 0x79>, <&audma1 0x7a>;
1215 dmas = <&audma0 0x11>, <&audma1 0x12>,
1216 <&audma0 0x7b>, <&audma1 0x7c>;
1221 dmas = <&audma0 0x13>, <&audma1 0x14>,
1222 <&audma0 0x7d>, <&audma1 0x7e>;
1231 reg = <0 0xec700000 0 0x10000>;
1262 reg = <0 0xec720000 0 0x10000>;
1293 reg = <0 0xee100000 0 0x328>;
1296 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
1297 <&dmac1 0xcd>, <&dmac1 0xce>;
1308 reg = <0 0xee140000 0 0x100>;
1311 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
1312 <&dmac1 0xc1>, <&dmac1 0xc2>;
1323 reg = <0 0xee160000 0 0x100>;
1326 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
1327 <&dmac1 0xd3>, <&dmac1 0xd4>;
1338 reg = <0 0xee200000 0 0x80>;
1341 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
1342 <&dmac1 0xd1>, <&dmac1 0xd2>;
1354 reg = <0 0xee700000 0 0x400>;
1361 #size-cells = <0>;
1368 #address-cells = <0>;
1370 reg = <0 0xf1001000 0 0x1000>,
1371 <0 0xf1002000 0 0x2000>,
1372 <0 0xf1004000 0 0x2000>,
1373 <0 0xf1006000 0 0x2000>;
1383 reg = <0 0xfe940000 0 0x2400>;
1392 reg = <0 0xfe944000 0 0x2400>;
1401 reg = <0 0xfeb00000 0 0x40000>;
1405 clock-names = "du.0", "du.1";
1407 reset-names = "du.0";
1412 #size-cells = <0>;
1414 port@0 {
1415 reg = <0>;
1430 reg = <0 0xfeb90000 0 0x1c>;
1439 #size-cells = <0>;
1441 port@0 {
1442 reg = <0>;
1457 reg = <0 0xff000044 0 4>;
1463 reg = <0 0xffca0000 0 0x1004>;
1477 reg = <0 0xe6130000 0 0x1004>;
1497 polling-delay-passive = <0>;
1498 polling-delay = <0>;
1505 hysteresis = <0>;
1526 #clock-cells = <0>;