Lines Matching +full:0 +full:xe6160000
40 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
71 L2_CA15: cache-controller-0 {
82 #clock-cells = <0>;
84 clock-frequency = <0>;
91 ranges = <0 0 0 0x1c000000>;
104 #clock-cells = <0>;
106 clock-frequency = <0>;
120 reg = <0 0xe6020000 0 0x0c>;
131 reg = <0 0xe6050000 0 0x50>;
135 gpio-ranges = <&pfc 0 0 29>;
146 reg = <0 0xe6051000 0 0x50>;
150 gpio-ranges = <&pfc 0 32 23>;
161 reg = <0 0xe6052000 0 0x50>;
165 gpio-ranges = <&pfc 0 64 32>;
176 reg = <0 0xe6053000 0 0x50>;
180 gpio-ranges = <&pfc 0 96 28>;
191 reg = <0 0xe6054000 0 0x50>;
195 gpio-ranges = <&pfc 0 128 17>;
206 reg = <0 0xe6055000 0 0x50>;
210 gpio-ranges = <&pfc 0 160 17>;
221 reg = <0 0xe6055100 0 0x50>;
225 gpio-ranges = <&pfc 0 192 17>;
236 reg = <0 0xe6055200 0 0x50>;
240 gpio-ranges = <&pfc 0 224 17>;
251 reg = <0 0xe6055300 0 0x50>;
255 gpio-ranges = <&pfc 0 256 17>;
266 reg = <0 0xe6055400 0 0x50>;
270 gpio-ranges = <&pfc 0 288 17>;
281 reg = <0 0xe6055500 0 0x50>;
285 gpio-ranges = <&pfc 0 320 32>;
296 reg = <0 0xe6055600 0 0x50>;
300 gpio-ranges = <&pfc 0 352 30>;
310 reg = <0 0xe6060000 0 0x144>;
315 reg = <0 0xe6150000 0 0x1000>;
319 #power-domain-cells = <0>;
325 reg = <0 0xe6152000 0 0x188>;
331 reg = <0 0xe6160000 0 0x0100>;
336 reg = <0 0xe6180000 0 0x0200>;
344 reg = <0 0xe61c0000 0 0x200>;
345 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
356 reg = <0 0xe61e0000 0 0x30>;
370 reg = <0 0xfff60000 0 0x30>;
385 reg = <0 0xfff70000 0 0x30>;
400 reg = <0 0xfff80000 0 0x30>;
415 reg = <0 0xe63a0000 0 0x12000>;
418 ranges = <0 0 0xe63a0000 0x12000>;
423 reg = <0 0xe63c0000 0 0x1000>;
426 ranges = <0 0 0xe63c0000 0x1000>;
428 smp-sram@0 {
430 reg = <0 0x100>;
438 reg = <0 0xe6508000 0 0x40>;
445 #size-cells = <0>;
452 reg = <0 0xe6518000 0 0x40>;
459 #size-cells = <0>;
466 reg = <0 0xe6530000 0 0x40>;
473 #size-cells = <0>;
480 reg = <0 0xe6540000 0 0x40>;
487 #size-cells = <0>;
494 reg = <0 0xe6520000 0 0x40>;
501 #size-cells = <0>;
508 reg = <0 0xe6528000 0 0x40>;
515 #size-cells = <0>;
521 #size-cells = <0>;
525 reg = <0 0xe60b0000 0 0x425>;
528 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
529 <&dmac1 0x77>, <&dmac1 0x78>;
539 reg = <0 0xe6700000 0 0x20000>;
572 reg = <0 0xe6720000 0 0x20000>;
605 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
612 #size-cells = <0>;
618 reg = <0 0xe6b10000 0 0x2c>;
621 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
622 <&dmac1 0x17>, <&dmac1 0x18>;
628 #size-cells = <0>;
635 reg = <0 0xe6e60000 0 64>;
640 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
641 <&dmac1 0x29>, <&dmac1 0x2a>;
651 reg = <0 0xe6e68000 0 64>;
656 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
657 <&dmac1 0x2d>, <&dmac1 0x2e>;
667 reg = <0 0xe6e58000 0 64>;
672 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
673 <&dmac1 0x2b>, <&dmac1 0x2c>;
683 reg = <0 0xe6ea8000 0 64>;
688 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
689 <&dmac1 0x2f>, <&dmac1 0x30>;
699 reg = <0 0xe62c0000 0 96>;
704 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
705 <&dmac1 0x39>, <&dmac1 0x3a>;
715 reg = <0 0xe62c8000 0 96>;
720 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
721 <&dmac1 0x4d>, <&dmac1 0x4e>;
731 reg = <0 0xe6e20000 0 0x0064>;
734 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
735 <&dmac1 0x51>, <&dmac1 0x52>;
740 #size-cells = <0>;
747 reg = <0 0xe6e10000 0 0x0064>;
750 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
751 <&dmac1 0x55>, <&dmac1 0x56>;
756 #size-cells = <0>;
763 reg = <0 0xe6e80000 0 0x1000>;
776 reg = <0 0xe6e88000 0 0x1000>;
789 reg = <0 0xe6ef0000 0 0x1000>;
800 reg = <0 0xe6ef1000 0 0x1000>;
811 reg = <0 0xe6ef2000 0 0x1000>;
822 reg = <0 0xe6ef3000 0 0x1000>;
833 reg = <0 0xe6ef4000 0 0x1000>;
844 reg = <0 0xe6ef5000 0 0x1000>;
855 reg = <0 0xee100000 0 0x328>;
856 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
857 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
858 <&dmac1 0xcd>, <&dmac1 0xce>;
870 reg = <0 0xf1001000 0 0x1000>,
871 <0 0xf1002000 0 0x2000>,
872 <0 0xf1004000 0 0x2000>,
873 <0 0xf1006000 0 0x2000>;
884 reg = <0 0xfe928000 0 0x8000>;
893 reg = <0 0xfe930000 0 0x8000>;
902 reg = <0 0xfe938000 0 0x8000>;
912 reg = <0 0xfe980000 0 0x10300>;
921 reg = <0 0xfeb00000 0 0x40000>;
925 clock-names = "du.0", "du.1";
927 reset-names = "du.0";
932 #size-cells = <0>;
934 port@0 {
935 reg = <0>;
949 reg = <0 0xff000044 0 4>;
955 reg = <0 0xffca0000 0 0x1004>;
969 reg = <0 0xe6130000 0 0x1004>;