Lines Matching +full:cmos +full:- +full:compatible
1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZ/G1H Qseven board development
9 /dts-v1/;
11 #include <dt-bindings/media/video-interfaces.h>
13 #include "r8a7742-iwg21d-q7.dts"
16 model = "iWave Systems RZ/G1H Qseven development platform with camera add-on";
17 compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";
27 mclk_cam1: mclk-cam1 {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <26000000>;
33 mclk_cam2: mclk-cam2 {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <26000000>;
39 mclk_cam3: mclk-cam3 {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <26000000>;
45 mclk_cam4: mclk-cam4 {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <26000000>;
52 compatible = "regulator-fixed";
53 regulator-name = "1P8V";
54 regulator-min-microvolt = <1800000>;
55 regulator-max-microvolt = <1800000>;
56 regulator-always-on;
60 compatible = "regulator-fixed";
61 regulator-name = "2P8V";
62 regulator-min-microvolt = <2800000>;
63 regulator-max-microvolt = <2800000>;
64 regulator-always-on;
74 pinctrl-0 = <&can0_pins>;
75 pinctrl-names = "default";
80 pinctrl-0 = <ðer_pins>;
81 pinctrl-names = "default";
83 phy-handle = <&phy1>;
84 renesas,ether-link-active-low;
87 phy1: ethernet-phy@1 {
88 compatible = "ethernet-phy-id0022.1560",
89 "ethernet-phy-ieee802.3-c22";
91 micrel,led-mode = <1>;
97 /delete-node/ qspi-en-hog;
100 vin2-en-hog {
101 gpio-hog;
103 output-high;
104 line-name = "VIN2_EN";
109 pinctrl-0 = <&hscif0_pins>;
110 pinctrl-names = "default";
111 uart-has-rtscts;
116 pinctrl-0 = <&i2c1_pins>;
117 pinctrl-names = "default";
120 clock-frequency = <400000>;
124 pinctrl-0 = <&i2c3_pins>;
125 pinctrl-names = "default";
128 clock-frequency = <400000>;
199 pinctrl-0 = <&scif0_pins>;
200 pinctrl-names = "default";
205 pinctrl-0 = <&scif1_pins>;
206 pinctrl-names = "default";
211 pinctrl-0 = <&scifb1_pins>;
212 pinctrl-names = "default";
215 rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
216 cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
225 /* 8bit CMOS Camera 1 (J13) */
231 #include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
232 //#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
241 pinctrl-0 = <&vin0_8bit_pins>;
242 pinctrl-names = "default";
246 remote-endpoint = <&cam0ep>;
247 bus-width = <8>;
248 bus-type = <MEDIA_BUS_TYPE_BT656>;
259 /* 8bit CMOS Camera 2 (J14) */
265 #include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
266 //#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
272 pinctrl-0 = <&vin1_8bit_pins>;
273 pinctrl-names = "default";
277 remote-endpoint = <&cam1ep>;
278 bus-width = <8>;
279 bus-type = <MEDIA_BUS_TYPE_BT656>;
291 /* 8bit CMOS Camera 3 (J12) */
297 #include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
298 //#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
303 pinctrl-0 = <&vin2_pins>;
304 pinctrl-names = "default";
308 remote-endpoint = <&cam2ep>;
309 bus-width = <8>;
310 data-shift = <8>;
311 bus-type = <MEDIA_BUS_TYPE_BT656>;
322 /* 8bit CMOS Camera 4 (J11) */
328 #include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
329 //#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
334 pinctrl-0 = <&vin3_pins>;
335 pinctrl-names = "default";
339 remote-endpoint = <&cam3ep>;
340 bus-width = <8>;
341 bus-type = <MEDIA_BUS_TYPE_BT656>;