Lines Matching +full:0 +full:xe6520000
21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 L2_CA15: cache-controller-0 {
66 reg = <0 0xe61e0000 0 0x30>;
79 reg = <0 0xfff80000 0 0x30>;
92 reg = <0 0xe6790000 0 0x10000>;
98 reg = <0 0xe67a0000 0 0x10000>;
104 #size-cells = <0>;
106 reg = <0 0xe60b0000 0 0x428>;
116 reg = <0 0xe6130000 0 0x1004>;
135 reg = <0 0xe61c0000 0 0x200>;
136 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
176 reg = <0 0xe61c0200 0 0x200>;
209 reg = <0 0xe6050000 0 0x9000>;
213 <&pfc 0 0 31>, <&pfc 32 32 9>,
220 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
221 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
222 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
223 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
224 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
225 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
226 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
227 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
228 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
229 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
230 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
231 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
232 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
233 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
234 <&irqc1 24 0>, <&irqc1 25 0>;
240 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
241 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
249 #size-cells = <0>;
251 reg = <0 0xe6500000 0 0x428>;
260 #size-cells = <0>;
262 reg = <0 0xe6510000 0 0x428>;
271 #size-cells = <0>;
273 reg = <0 0xe6520000 0 0x428>;
282 #size-cells = <0>;
284 reg = <0 0xe6530000 0 0x428>;
293 #size-cells = <0>;
295 reg = <0 0xe6540000 0 0x428>;
304 #size-cells = <0>;
306 reg = <0 0xe6550000 0 0x428>;
315 #size-cells = <0>;
317 reg = <0 0xe6560000 0 0x428>;
326 #size-cells = <0>;
328 reg = <0 0xe6570000 0 0x428>;
337 reg = <0 0xe6c20000 0 0x100>;
347 reg = <0 0xe6c30000 0 0x100>;
357 reg = <0 0xe6c40000 0 0x100>;
367 reg = <0 0xe6c50000 0 0x100>;
377 reg = <0 0xe6ce0000 0 0x100>;
387 reg = <0 0xe6cf0000 0 0x100>;
397 reg = <0 0xee100000 0 0x100>;
407 reg = <0 0xee120000 0 0x100>;
417 reg = <0 0xee140000 0 0x100>;
427 reg = <0 0xee200000 0 0x80>;
437 reg = <0 0xee220000 0 0x80>;
448 #address-cells = <0>;
450 reg = <0 0xf1001000 0 0x1000>,
451 <0 0xf1002000 0 0x2000>,
452 <0 0xf1004000 0 0x2000>,
453 <0 0xf1006000 0 0x2000>;
465 ranges = <0 0 0 0x20000000>;
466 reg = <0 0xfec10000 0 0x400>;
479 #clock-cells = <0>;
481 clock-frequency = <0>;
485 #clock-cells = <0>;
487 clock-frequency = <0>;
491 #clock-cells = <0>;
493 clock-frequency = <0>;
497 #clock-cells = <0>;
499 clock-frequency = <0>;
503 #clock-cells = <0>;
505 clock-frequency = <0>;
511 reg = <0 0xe6150000 0 0x10000>;
523 reg = <0 0xe6150010 0 4>;
524 clocks = <&pll1_div2_clk>, <0>,
525 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
526 #clock-cells = <0>;
531 reg = <0 0xe6150074 0 4>;
533 <0>, <&extal2_clk>;
534 #clock-cells = <0>;
538 reg = <0 0xe6150078 0 4>;
540 <0>, <&extal2_clk>;
541 #clock-cells = <0>;
545 reg = <0 0xe615007c 0 4>;
547 <0>, <&extal2_clk>;
548 #clock-cells = <0>;
552 reg = <0 0xe6150240 0 4>;
554 <0>, <&extal2_clk>;
555 #clock-cells = <0>;
559 reg = <0 0xe6150244 0 4>;
561 <0>, <&extal2_clk>;
562 #clock-cells = <0>;
566 reg = <0 0xe6150008 0 4>;
568 <0>, <&extal2_clk>, <&main_div2_clk>,
569 <&extalr_clk>, <0>, <0>;
570 #clock-cells = <0>;
574 reg = <0 0xe615000c 0 4>;
576 <0>, <&extal2_clk>, <&main_div2_clk>,
577 <&extalr_clk>, <0>, <0>;
578 #clock-cells = <0>;
582 reg = <0 0xe615001c 0 4>;
584 <0>, <&extal2_clk>, <&main_div2_clk>,
585 <&extalr_clk>, <0>, <0>;
586 #clock-cells = <0>;
590 reg = <0 0xe6150014 0 4>;
592 <0>, <&extal2_clk>, <&main_div2_clk>,
593 <&extalr_clk>, <0>, <0>;
594 #clock-cells = <0>;
598 reg = <0 0xe6150034 0 4>;
600 <0>, <&extal2_clk>, <&main_div2_clk>,
601 <&extalr_clk>, <0>, <0>;
602 #clock-cells = <0>;
606 reg = <0 0xe6150018 0 4>;
608 <&fsiack_clk>, <0>;
609 #clock-cells = <0>;
613 reg = <0 0xe6150090 0 4>;
615 <&fsibck_clk>, <0>;
616 #clock-cells = <0>;
620 reg = <0 0xe6150080 0 4>;
623 #clock-cells = <0>;
627 reg = <0 0xe6150098 0 4>;
629 #clock-cells = <0>;
633 reg = <0 0xe615026c 0 4>;
635 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
636 #clock-cells = <0>;
640 reg = <0 0xe6150094 0 4>;
643 #clock-cells = <0>;
650 #clock-cells = <0>;
657 #clock-cells = <0>;
664 #clock-cells = <0>;
671 #clock-cells = <0>;
678 #clock-cells = <0>;
686 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
697 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
713 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
736 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
751 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
764 reg = <0 0xff000044 0 4>;
769 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
774 #size-cells = <0>;
775 #power-domain-cells = <0>;
777 pd_c4: c4@0 {
778 reg = <0>;
780 #size-cells = <0>;
781 #power-domain-cells = <0>;
785 #power-domain-cells = <0>;
790 #power-domain-cells = <0>;
796 #size-cells = <0>;
797 #power-domain-cells = <0>;
801 #power-domain-cells = <0>;
808 #size-cells = <0>;
809 #power-domain-cells = <0>;
813 #power-domain-cells = <0>;
820 #size-cells = <0>;
821 #power-domain-cells = <0>;
825 #power-domain-cells = <0>;
832 #power-domain-cells = <0>;
837 #power-domain-cells = <0>;
842 #power-domain-cells = <0>;
848 #size-cells = <0>;
849 #power-domain-cells = <0>;
853 #power-domain-cells = <0>;
859 #power-domain-cells = <0>;
864 #power-domain-cells = <0>;
870 #size-cells = <0>;
871 #power-domain-cells = <0>;
875 #power-domain-cells = <0>;
880 #power-domain-cells = <0>;
886 #power-domain-cells = <0>;
892 #size-cells = <0>;
893 #power-domain-cells = <0>;
897 #power-domain-cells = <0>;
902 #power-domain-cells = <0>;