Lines Matching +full:msm +full:- +full:uartdm
1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
21 interrupt-parent = <&intc>;
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 clock-frequency = <76800000>;
32 clock-output-names = "xo_board";
33 #clock-cells = <0>;
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 clock-frequency = <32764>;
39 clock-output-names = "sleep_clk";
40 #clock-cells = <0>;
43 nand_clk_dummy: nand-clk-dummy {
44 compatible = "fixed-clock";
45 clock-frequency = <32764>;
46 #clock-cells = <0>;
51 #address-cells = <1>;
52 #size-cells = <0>;
56 compatible = "arm,cortex-a7";
58 enable-method = "psci";
60 power-domains = <&rpmhpd SDX65_CX_AO>;
61 power-domain-names = "rpmhpd";
62 operating-points-v2 = <&cpu_opp_table>;
68 compatible = "qcom,scm-sdx65", "qcom,scm";
72 mc_virt: interconnect-mc-virt {
73 compatible = "qcom,sdx65-mc-virt";
74 #interconnect-cells = <1>;
75 qcom,bcm-voters = <&apps_bcm_voter>;
78 cpu_opp_table: opp-table-cpu {
79 compatible = "operating-points-v2";
80 opp-shared;
82 opp-345600000 {
83 opp-hz = /bits/ 64 <345600000>;
84 required-opps = <&rpmhpd_opp_low_svs>;
87 opp-576000000 {
88 opp-hz = /bits/ 64 <576000000>;
89 required-opps = <&rpmhpd_opp_svs>;
92 opp-1094400000 {
93 opp-hz = /bits/ 64 <1094400000>;
94 required-opps = <&rpmhpd_opp_nom>;
97 opp-1497600000 {
98 opp-hz = /bits/ 64 <1497600000>;
99 required-opps = <&rpmhpd_opp_turbo>;
104 compatible = "arm,psci-1.0";
108 reserved_memory: reserved-memory {
109 #address-cells = <1>;
110 #size-cells = <1>;
114 no-map;
119 no-map;
124 no-map;
129 no-map;
134 no-map;
142 no-map;
145 cmd_db: reserved-memory@8fee0000 {
146 compatible = "qcom,cmd-db";
148 no-map;
152 no-map;
157 no-map;
162 no-map;
167 smp2p-mpss {
172 qcom,local-pid = <0>;
173 qcom,remote-pid = <1>;
175 modem_smp2p_out: master-kernel {
176 qcom,entry-name = "master-kernel";
177 #qcom,smem-state-cells = <1>;
180 modem_smp2p_in: slave-kernel {
181 qcom,entry-name = "slave-kernel";
182 interrupt-controller;
183 #interrupt-cells = <2>;
186 ipa_smp2p_out: ipa-ap-to-modem {
187 qcom,entry-name = "ipa";
188 #qcom,smem-state-cells = <1>;
191 ipa_smp2p_in: ipa-modem-to-ap {
192 qcom,entry-name = "ipa";
193 interrupt-controller;
194 #interrupt-cells = <2>;
199 #address-cells = <1>;
200 #size-cells = <1>;
202 compatible = "simple-bus";
204 gcc: clock-controller@100000 {
205 compatible = "qcom,gcc-sdx65";
212 clock-names = "bi_tcxo",
217 #power-domain-cells = <1>;
218 #clock-cells = <1>;
219 #reset-cells = <1>;
223 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
227 clock-names = "core", "iface";
232 compatible = "qcom,sdx65-usb-hs-phy",
233 "qcom,usb-snps-hs-7nm-phy";
235 #phy-cells = <0>;
237 clock-names = "ref";
243 compatible = "qcom,sdx65-qmp-usb3-uni-phy";
250 clock-names = "aux",
254 clock-output-names = "usb3_uni_phy_pipe_clk_src";
255 #clock-cells = <0>;
256 #phy-cells = <0>;
260 reset-names = "phy",
268 compatible = "qcom,sdx65-system-noc";
270 #interconnect-cells = <1>;
271 qcom,bcm-voters = <&apps_bcm_voter>;
274 qpic_bam: dma-controller@1b04000 {
275 compatible = "qcom,bam-v1.7.0";
279 clock-names = "bam_clk";
280 #dma-cells = <1>;
282 qcom,controlled-remotely;
286 qpic_nand: nand-controller@1b30000 {
287 compatible = "qcom,sdx55-nand";
289 #address-cells = <1>;
290 #size-cells = <0>;
293 clock-names = "core", "aon";
298 dma-names = "tx", "rx", "cmd";
302 pcie_ep: pcie-ep@1c00000 {
303 compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
310 reg-names = "parf",
317 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
326 clock-names = "aux",
336 interrupt-names = "global", "doorbell";
339 reset-names = "core";
341 power-domains = <&gcc PCIE_GDSC>;
344 phy-names = "pciephy";
346 max-link-speed = <3>;
347 num-lanes = <2>;
353 compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
361 clock-names = "aux",
368 reset-names = "phy";
370 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
371 assigned-clock-rates = <100000000>;
373 power-domains = <&gcc PCIE_GDSC>;
375 #clock-cells = <0>;
376 clock-output-names = "pcie_pipe_clk";
378 #phy-cells = <0>;
384 compatible = "qcom,tcsr-mutex";
386 #hwlock-cells = <1>;
390 compatible = "qcom,sdx65-tcsr", "syscon";
395 compatible = "qcom,sdx65-ipa";
400 reg-names = "ipa-reg",
401 "ipa-shared",
404 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
408 interrupt-names = "ipa",
410 "ipa-clock-query",
411 "ipa-setup-ready";
417 clock-names = "core";
421 interconnect-names = "memory",
424 qcom,smem-states = <&ipa_smp2p_out 0>,
426 qcom,smem-state-names = "ipa-clock-enabled-valid",
427 "ipa-clock-enabled";
433 compatible = "qcom,sdx55-mpss-pas";
436 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
442 interrupt-names = "wdog", "fatal", "ready", "handover",
443 "stop-ack", "shutdown-ack";
446 clock-names = "xo";
448 power-domains = <&rpmhpd SDX65_CX>,
450 power-domain-names = "cx", "mss";
452 qcom,smem-states = <&modem_smp2p_out 0>;
453 qcom,smem-state-names = "stop";
457 glink-edge {
460 qcom,remote-pid = <1>;
466 compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
468 reg-names = "hc";
471 interrupt-names = "hc_irq", "pwr_irq";
474 clock-names = "iface", "core";
479 compatible = "qcom,sdx65-mem-noc";
481 #interconnect-cells = <1>;
482 qcom,bcm-voters = <&apps_bcm_voter>;
486 compatible = "qcom,sdx65-dwc3", "qcom,dwc3";
488 #address-cells = <1>;
489 #size-cells = <1>;
497 clock-names = "cfg_noc", "core", "iface", "sleep",
500 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
502 assigned-clock-rates = <19200000>, <200000000>;
504 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
509 interrupt-names = "pwr_event",
515 power-domains = <&gcc USB30_GDSC>;
529 phy-names = "usb2-phy", "usb3-phy";
539 compatible = "qcom,spmi-pmic-arb";
545 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
546 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
547 interrupt-names = "periph_irq";
548 interrupt-controller;
549 #interrupt-cells = <4>;
550 #address-cells = <2>;
551 #size-cells = <0>;
557 compatible = "qcom,sdx65-tlmm";
560 gpio-controller;
561 #gpio-cells = <2>;
562 gpio-ranges = <&tlmm 0 0 109>;
563 interrupt-controller;
564 interrupt-parent = <&intc>;
565 #interrupt-cells = <2>;
568 pdc: interrupt-controller@b210000 {
569 compatible = "qcom,sdx65-pdc", "qcom,pdc";
571 qcom,pdc-ranges = <0 147 52>, <52 266 32>;
572 #interrupt-cells = <2>;
573 interrupt-parent = <&intc>;
574 interrupt-controller;
578 compatible = "qcom,sdx65-imem", "syscon", "simple-mfd";
581 #address-cells = <1>;
582 #size-cells = <1>;
584 pil-reloc@94c {
585 compatible = "qcom,pil-reloc-info";
591 compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500";
593 #iommu-cells = <2>;
594 #global-interrupts = <1>;
630 intc: interrupt-controller@17800000 {
631 compatible = "qcom,msm-qgic2";
632 interrupt-controller;
633 interrupt-parent = <&intc>;
634 #interrupt-cells = <3>;
640 compatible = "qcom,sdx55-a7pll";
643 clock-names = "bi_tcxo";
644 #clock-cells = <0>;
648 compatible = "qcom,sdx55-apcs-gcc", "syscon";
650 #mbox-cells = <1>;
652 clock-names = "ref", "pll", "aux";
653 #clock-cells = <0>;
657 compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt";
663 #address-cells = <1>;
664 #size-cells = <1>;
666 compatible = "arm,armv7-timer-mem";
668 clock-frequency = <19200000>;
671 frame-number = <0>;
679 frame-number = <1>;
686 frame-number = <2>;
693 frame-number = <3>;
700 frame-number = <4>;
707 frame-number = <5>;
714 frame-number = <6>;
721 frame-number = <7>;
730 compatible = "qcom,rpmh-rsc";
733 reg-names = "drv-0", "drv-1";
736 qcom,tcs-offset = <0xd00>;
737 qcom,drv-id = <1>;
738 qcom,tcs-config = <ACTIVE_TCS 2>,
743 rpmhcc: clock-controller {
744 compatible = "qcom,sdx65-rpmh-clk";
745 #clock-cells = <1>;
746 clock-names = "xo";
750 rpmhpd: power-controller {
751 compatible = "qcom,sdx65-rpmhpd";
752 #power-domain-cells = <1>;
753 operating-points-v2 = <&rpmhpd_opp_table>;
755 rpmhpd_opp_table: opp-table {
756 compatible = "operating-points-v2";
759 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
763 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
767 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
771 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
775 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
779 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
783 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
787 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
791 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
795 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
800 apps_bcm_voter: bcm-voter {
801 compatible = "qcom,bcm-voter";
808 compatible = "arm,armv7-timer";
813 clock-frequency = <19200000>;