Lines Matching +full:tcs +full:- +full:config
1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interconnect/qcom,sdx55.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
21 interrupt-parent = <&intc>;
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <38400000>;
33 clock-output-names = "xo_board";
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <32000>;
42 nand_clk_dummy: nand-clk-dummy {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <32000>;
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a7";
57 enable-method = "psci";
59 power-domains = <&rpmhpd SDX55_CX>;
60 power-domain-names = "rpmhpd";
61 operating-points-v2 = <&cpu_opp_table>;
67 compatible = "qcom,scm-sdx55", "qcom,scm";
71 cpu_opp_table: opp-table-cpu {
72 compatible = "operating-points-v2";
73 opp-shared;
75 opp-345600000 {
76 opp-hz = /bits/ 64 <345600000>;
77 required-opps = <&rpmhpd_opp_low_svs>;
80 opp-576000000 {
81 opp-hz = /bits/ 64 <576000000>;
82 required-opps = <&rpmhpd_opp_svs>;
85 opp-1094400000 {
86 opp-hz = /bits/ 64 <1094400000>;
87 required-opps = <&rpmhpd_opp_nom>;
90 opp-1555200000 {
91 opp-hz = /bits/ 64 <1555200000>;
92 required-opps = <&rpmhpd_opp_turbo>;
97 compatible = "arm,psci-1.0";
101 reserved-memory {
102 #address-cells = <1>;
103 #size-cells = <1>;
107 no-map;
112 no-map;
117 no-map;
122 no-map;
127 no-map;
132 compatible = "qcom,cmd-db";
134 no-map;
138 no-map;
143 no-map;
148 no-map;
155 memory-region = <&smem_mem>;
159 smp2p-mpss {
164 qcom,local-pid = <0>;
165 qcom,remote-pid = <1>;
167 modem_smp2p_out: master-kernel {
168 qcom,entry-name = "master-kernel";
169 #qcom,smem-state-cells = <1>;
172 modem_smp2p_in: slave-kernel {
173 qcom,entry-name = "slave-kernel";
174 interrupt-controller;
175 #interrupt-cells = <2>;
178 ipa_smp2p_out: ipa-ap-to-modem {
179 qcom,entry-name = "ipa";
180 #qcom,smem-state-cells = <1>;
183 ipa_smp2p_in: ipa-modem-to-ap {
184 qcom,entry-name = "ipa";
185 interrupt-controller;
186 #interrupt-cells = <2>;
191 #address-cells = <1>;
192 #size-cells = <1>;
194 compatible = "simple-bus";
196 gcc: clock-controller@100000 {
197 compatible = "qcom,gcc-sdx55";
199 #clock-cells = <1>;
200 #reset-cells = <1>;
201 #power-domain-cells = <1>;
202 clock-names = "bi_tcxo", "sleep_clk";
207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
212 clock-names = "core", "iface";
217 compatible = "qcom,sdx55-usb-hs-phy",
218 "qcom,usb-snps-hs-7nm-phy";
221 #phy-cells = <0>;
224 clock-names = "ref";
230 compatible = "qcom,sdx55-qmp-usb3-uni-phy";
237 clock-names = "aux",
241 clock-output-names = "usb3_uni_phy_pipe_clk_src";
242 #clock-cells = <0>;
243 #phy-cells = <0>;
247 reset-names = "phy",
254 compatible = "qcom,sdx55-mc-virt";
256 #interconnect-cells = <1>;
257 qcom,bcm-voters = <&apps_bcm_voter>;
261 compatible = "qcom,sdx55-mem-noc";
263 #interconnect-cells = <1>;
264 qcom,bcm-voters = <&apps_bcm_voter>;
268 compatible = "qcom,sdx55-system-noc";
270 #interconnect-cells = <1>;
271 qcom,bcm-voters = <&apps_bcm_voter>;
274 qpic_bam: dma-controller@1b04000 {
275 compatible = "qcom,bam-v1.7.0";
279 clock-names = "bam_clk";
280 #dma-cells = <1>;
282 qcom,controlled-remotely;
286 qpic_nand: nand-controller@1b30000 {
287 compatible = "qcom,sdx55-nand";
289 #address-cells = <1>;
290 #size-cells = <0>;
293 clock-names = "core", "aon";
298 dma-names = "tx", "rx", "cmd";
303 compatible = "qcom,pcie-sdx55";
309 reg-names = "parf",
313 "config";
315 linux,pci-domain = <0>;
316 bus-range = <0x00 0xff>;
317 num-lanes = <1>;
319 #address-cells = <3>;
320 #size-cells = <2>;
333 interrupt-names = "msi",
341 #interrupt-cells = <1>;
342 interrupt-map-mask = <0 0 0 0x7>;
343 interrupt-map = <0 0 0 1 &intc 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
355 clock-names = "pipe",
363 assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
364 assigned-clock-rates = <19200000>;
366 iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
373 reset-names = "pci";
375 power-domains = <&gcc PCIE_GDSC>;
378 phy-names = "pciephy";
385 bus-range = <0x01 0xff>;
387 #address-cells = <3>;
388 #size-cells = <2>;
393 pcie_ep: pcie-ep@1c00000 {
394 compatible = "qcom,sdx55-pcie-ep";
401 reg-names = "parf",
408 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
417 clock-names = "aux",
427 interrupt-names = "global",
431 interconnect-names = "pcie-mem";
434 reset-names = "core";
435 power-domains = <&gcc PCIE_GDSC>;
437 phy-names = "pciephy";
438 max-link-speed = <3>;
439 num-lanes = <2>;
445 compatible = "qcom,sdx55-qmp-pcie-phy";
447 #address-cells = <1>;
448 #size-cells = <1>;
455 clock-names = "aux",
461 clock-output-names = "pcie_pipe_clk";
462 #clock-cells = <0>;
464 #phy-cells = <0>;
467 reset-names = "phy";
469 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
470 assigned-clock-rates = <100000000>;
476 compatible = "qcom,sdx55-ipa";
483 reg-names = "ipa-reg",
484 "ipa-shared",
487 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
491 interrupt-names = "ipa",
493 "ipa-clock-query",
494 "ipa-setup-ready";
497 clock-names = "core";
502 interconnect-names = "memory",
504 "config";
506 qcom,smem-states = <&ipa_smp2p_out 0>,
508 qcom,smem-state-names = "ipa-clock-enabled-valid",
509 "ipa-clock-enabled";
515 compatible = "qcom,tcsr-mutex";
517 #hwlock-cells = <1>;
521 compatible = "qcom,sdx55-tcsr", "syscon";
526 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
530 interrupt-names = "hc_irq", "pwr_irq";
533 clock-names = "iface", "core";
538 compatible = "qcom,sdx55-mpss-pas";
541 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
547 interrupt-names = "wdog", "fatal", "ready", "handover",
548 "stop-ack", "shutdown-ack";
551 clock-names = "xo";
553 power-domains = <&rpmhpd SDX55_CX>,
555 power-domain-names = "cx", "mss";
557 qcom,smem-states = <&modem_smp2p_out 0>;
558 qcom,smem-state-names = "stop";
562 glink-edge {
565 qcom,remote-pid = <1>;
571 compatible = "qcom,sdx55-dwc3", "qcom,dwc3";
574 #address-cells = <1>;
575 #size-cells = <1>;
583 clock-names = "cfg_noc",
589 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
591 assigned-clock-rates = <19200000>, <200000000>;
593 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
598 interrupt-names = "pwr_event",
604 power-domains = <&gcc USB30_GDSC>;
616 phy-names = "usb2-phy", "usb3-phy";
620 pdc: interrupt-controller@b210000 {
621 compatible = "qcom,sdx55-pdc", "qcom,pdc";
623 qcom,pdc-ranges = <0 179 52>;
624 #interrupt-cells = <2>;
625 interrupt-parent = <&intc>;
626 interrupt-controller;
635 compatible = "qcom,spmi-pmic-arb";
641 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
642 interrupt-names = "periph_irq";
646 #address-cells = <2>;
647 #size-cells = <0>;
648 interrupt-controller;
649 #interrupt-cells = <4>;
653 compatible = "qcom,sdx55-pinctrl";
656 gpio-controller;
657 #gpio-cells = <2>;
658 interrupt-controller;
659 #interrupt-cells = <2>;
660 gpio-ranges = <&tlmm 0 0 108>;
664 compatible = "qcom,sdx55-imem", "syscon", "simple-mfd";
667 #address-cells = <1>;
668 #size-cells = <1>;
672 pil-reloc@94c {
673 compatible = "qcom,pil-reloc-info";
679 compatible = "qcom,sdx55-smmu-500", "qcom,smmu-500", "arm,mmu-500";
681 #iommu-cells = <2>;
682 #global-interrupts = <1>;
702 intc: interrupt-controller@17800000 {
703 compatible = "qcom,msm-qgic2";
704 interrupt-controller;
705 interrupt-parent = <&intc>;
706 #interrupt-cells = <3>;
712 compatible = "qcom,sdx55-a7pll";
715 clock-names = "bi_tcxo";
716 #clock-cells = <0>;
720 compatible = "qcom,sdx55-apcs-gcc", "syscon";
722 #mbox-cells = <1>;
724 clock-names = "ref", "pll", "aux";
725 #clock-cells = <0>;
729 compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
735 #address-cells = <1>;
736 #size-cells = <1>;
738 compatible = "arm,armv7-timer-mem";
740 clock-frequency = <19200000>;
743 frame-number = <0>;
751 frame-number = <1>;
758 frame-number = <2>;
765 frame-number = <3>;
772 frame-number = <4>;
779 frame-number = <5>;
786 frame-number = <6>;
793 frame-number = <7>;
801 compatible = "qcom,rpmh-rsc";
803 reg-names = "drv-0", "drv-1";
806 qcom,tcs-offset = <0xd00>;
807 qcom,drv-id = <1>;
808 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>,
811 rpmhcc: clock-controller {
812 compatible = "qcom,sdx55-rpmh-clk";
813 #clock-cells = <1>;
814 clock-names = "xo";
818 rpmhpd: power-controller {
819 compatible = "qcom,sdx55-rpmhpd";
820 #power-domain-cells = <1>;
821 operating-points-v2 = <&rpmhpd_opp_table>;
823 rpmhpd_opp_table: opp-table {
824 compatible = "operating-points-v2";
827 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
831 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
835 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
839 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
843 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
847 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
851 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
855 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
859 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
863 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
868 apps_bcm_voter: bcm-voter {
869 compatible = "qcom,bcm-voter";
875 compatible = "arm,armv7-timer";
880 clock-frequency = <19200000>;