Lines Matching +full:tcsr +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
11 #include <dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
16 interrupt-parent = <&intc>;
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <19200000>;
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <32768>;
35 #address-cells = <1>;
36 #size-cells = <0>;
41 enable-method = "qcom,kpss-acc-v2";
43 reg = <0>;
44 next-level-cache = <&l2>;
47 cpu-idle-states = <&cpu_spc>;
52 enable-method = "qcom,kpss-acc-v2";
54 reg = <1>;
55 next-level-cache = <&l2>;
58 cpu-idle-states = <&cpu_spc>;
63 enable-method = "qcom,kpss-acc-v2";
65 reg = <2>;
66 next-level-cache = <&l2>;
69 cpu-idle-states = <&cpu_spc>;
74 enable-method = "qcom,kpss-acc-v2";
76 reg = <3>;
77 next-level-cache = <&l2>;
80 cpu-idle-states = <&cpu_spc>;
83 l2: l2-cache {
85 cache-level = <2>;
86 cache-unified;
90 idle-states {
91 cpu_spc: cpu-spc {
92 compatible = "qcom,idle-state-spc",
93 "arm,idle-state";
94 entry-latency-us = <150>;
95 exit-latency-us = <200>;
96 min-residency-us = <2000>;
103 compatible = "qcom,scm-msm8974", "qcom,scm";
105 clock-names = "core", "bus", "iface";
111 reg = <0x0 0x0>;
115 compatible = "qcom,krait-pmu";
120 compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc";
122 master-stats {
123 compatible = "qcom,rpm-master-stats";
124 qcom,rpm-msg-ram = <&apss_master_stats>,
128 qcom,master-names = "APSS",
134 smd-edge {
137 qcom,smd-edge = <15>;
139 rpm_requests: rpm-requests {
140 compatible = "qcom,rpm-msm8974", "qcom,smd-rpm";
141 qcom,smd-channels = "rpm_requests";
143 rpmcc: clock-controller {
144 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
145 #clock-cells = <1>;
147 clock-names = "xo";
153 reserved_memory: reserved-memory {
154 #address-cells = <1>;
155 #size-cells = <1>;
159 reg = <0x08000000 0x5100000>;
160 no-map;
164 reg = <0x0d100000 0x100000>;
165 no-map;
169 reg = <0x0d200000 0xa00000>;
170 no-map;
174 reg = <0x0dc00000 0x1900000>;
175 no-map;
179 reg = <0x0f500000 0x500000>;
180 no-map;
184 reg = <0xfa00000 0x200000>;
185 no-map;
189 reg = <0x0fc00000 0x160000>;
190 no-map;
194 reg = <0x0fd60000 0x20000>;
195 no-map;
199 compatible = "qcom,rmtfs-mem";
200 reg = <0x0fd80000 0x180000>;
201 no-map;
203 qcom,client-id = <1>;
210 memory-region = <&smem_region>;
211 qcom,rpm-msg-ram = <&rpm_msg_ram>;
216 smp2p-adsp {
220 interrupt-parent = <&intc>;
225 qcom,local-pid = <0>;
226 qcom,remote-pid = <2>;
228 adsp_smp2p_out: master-kernel {
229 qcom,entry-name = "master-kernel";
230 #qcom,smem-state-cells = <1>;
233 adsp_smp2p_in: slave-kernel {
234 qcom,entry-name = "slave-kernel";
236 interrupt-controller;
237 #interrupt-cells = <2>;
241 smp2p-modem {
245 interrupt-parent = <&intc>;
250 qcom,local-pid = <0>;
251 qcom,remote-pid = <1>;
253 modem_smp2p_out: master-kernel {
254 qcom,entry-name = "master-kernel";
255 #qcom,smem-state-cells = <1>;
258 modem_smp2p_in: slave-kernel {
259 qcom,entry-name = "slave-kernel";
261 interrupt-controller;
262 #interrupt-cells = <2>;
266 smp2p-wcnss {
270 interrupt-parent = <&intc>;
275 qcom,local-pid = <0>;
276 qcom,remote-pid = <4>;
278 wcnss_smp2p_out: master-kernel {
279 qcom,entry-name = "master-kernel";
281 #qcom,smem-state-cells = <1>;
284 wcnss_smp2p_in: slave-kernel {
285 qcom,entry-name = "slave-kernel";
287 interrupt-controller;
288 #interrupt-cells = <2>;
295 #address-cells = <1>;
296 #size-cells = <0>;
301 reg = <0>;
303 #qcom,smem-state-cells = <1>;
307 reg = <1>;
310 interrupt-controller;
311 #interrupt-cells = <2>;
315 reg = <2>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
323 reg = <7>;
326 interrupt-controller;
327 #interrupt-cells = <2>;
332 #address-cells = <1>;
333 #size-cells = <1>;
335 compatible = "simple-bus";
337 intc: interrupt-controller@f9000000 {
338 compatible = "qcom,msm-qgic2";
339 interrupt-controller;
340 #interrupt-cells = <3>;
341 reg = <0xf9000000 0x1000>,
346 compatible = "qcom,msm8974-apcs-kpss-global",
347 "qcom,msm8994-apcs-kpss-global", "syscon";
348 reg = <0xf9011000 0x1000>;
349 #mbox-cells = <1>;
352 saw_l2: power-manager@f9012000 {
353 compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2";
354 reg = <0xf9012000 0x1000>;
358 compatible = "qcom,apss-wdt-msm8974", "qcom,kpss-wdt";
359 reg = <0xf9017000 0x1000>;
366 #address-cells = <1>;
367 #size-cells = <1>;
369 compatible = "arm,armv7-timer-mem";
370 reg = <0xf9020000 0x1000>;
371 clock-frequency = <19200000>;
374 frame-number = <0>;
377 reg = <0xf9021000 0x1000>,
382 frame-number = <1>;
384 reg = <0xf9023000 0x1000>;
389 frame-number = <2>;
391 reg = <0xf9024000 0x1000>;
396 frame-number = <3>;
398 reg = <0xf9025000 0x1000>;
403 frame-number = <4>;
405 reg = <0xf9026000 0x1000>;
410 frame-number = <5>;
412 reg = <0xf9027000 0x1000>;
417 frame-number = <6>;
419 reg = <0xf9028000 0x1000>;
424 acc0: power-manager@f9088000 {
425 compatible = "qcom,kpss-acc-v2";
426 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
429 saw0: power-manager@f9089000 {
430 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
431 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
434 acc1: power-manager@f9098000 {
435 compatible = "qcom,kpss-acc-v2";
436 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
439 saw1: power-manager@f9099000 {
440 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
441 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
444 acc2: power-manager@f90a8000 {
445 compatible = "qcom,kpss-acc-v2";
446 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
449 saw2: power-manager@f90a9000 {
450 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
451 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
454 acc3: power-manager@f90b8000 {
455 compatible = "qcom,kpss-acc-v2";
456 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
459 saw3: power-manager@f90b9000 {
460 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
461 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
465 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
466 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
467 reg-names = "hc", "core";
470 interrupt-names = "hc_irq", "pwr_irq";
474 clock-names = "iface", "core", "xo";
475 bus-width = <8>;
476 non-removable;
482 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
483 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
484 reg-names = "hc", "core";
487 interrupt-names = "hc_irq", "pwr_irq";
491 clock-names = "iface", "core", "xo";
492 bus-width = <4>;
494 #address-cells = <1>;
495 #size-cells = <0>;
501 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
502 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
503 reg-names = "hc", "core";
506 interrupt-names = "hc_irq", "pwr_irq";
510 clock-names = "iface", "core", "xo";
511 bus-width = <4>;
513 #address-cells = <1>;
514 #size-cells = <0>;
520 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
521 reg = <0xf991d000 0x1000>;
524 clock-names = "core", "iface";
529 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
530 reg = <0xf991e000 0x1000>;
533 clock-names = "core", "iface";
534 pinctrl-names = "default";
535 pinctrl-0 = <&blsp1_uart2_default>;
541 compatible = "qcom,i2c-qup-v2.1.1";
542 reg = <0xf9923000 0x1000>;
545 clock-names = "core", "iface";
546 pinctrl-names = "default", "sleep";
547 pinctrl-0 = <&blsp1_i2c1_default>;
548 pinctrl-1 = <&blsp1_i2c1_sleep>;
549 #address-cells = <1>;
550 #size-cells = <0>;
555 compatible = "qcom,i2c-qup-v2.1.1";
556 reg = <0xf9924000 0x1000>;
559 clock-names = "core", "iface";
560 pinctrl-names = "default", "sleep";
561 pinctrl-0 = <&blsp1_i2c2_default>;
562 pinctrl-1 = <&blsp1_i2c2_sleep>;
563 #address-cells = <1>;
564 #size-cells = <0>;
569 compatible = "qcom,i2c-qup-v2.1.1";
570 reg = <0xf9925000 0x1000>;
573 clock-names = "core", "iface";
574 pinctrl-names = "default", "sleep";
575 pinctrl-0 = <&blsp1_i2c3_default>;
576 pinctrl-1 = <&blsp1_i2c3_sleep>;
577 #address-cells = <1>;
578 #size-cells = <0>;
583 compatible = "qcom,i2c-qup-v2.1.1";
584 reg = <0xf9928000 0x1000>;
587 clock-names = "core", "iface";
588 pinctrl-names = "default", "sleep";
589 pinctrl-0 = <&blsp1_i2c6_default>;
590 pinctrl-1 = <&blsp1_i2c6_sleep>;
591 #address-cells = <1>;
592 #size-cells = <0>;
595 blsp2_dma: dma-controller@f9944000 {
596 compatible = "qcom,bam-v1.4.0";
597 reg = <0xf9944000 0x19000>;
600 clock-names = "bam_clk";
601 #dma-cells = <1>;
606 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
607 reg = <0xf995d000 0x1000>;
610 clock-names = "core", "iface";
611 pinctrl-names = "default", "sleep";
612 pinctrl-0 = <&blsp2_uart1_default>;
613 pinctrl-1 = <&blsp2_uart1_sleep>;
618 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
619 reg = <0xf995e000 0x1000>;
622 clock-names = "core", "iface";
627 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
628 reg = <0xf9960000 0x1000>;
631 clock-names = "core", "iface";
632 pinctrl-names = "default";
633 pinctrl-0 = <&blsp2_uart4_default>;
639 compatible = "qcom,i2c-qup-v2.1.1";
640 reg = <0xf9964000 0x1000>;
643 clock-names = "core", "iface";
644 pinctrl-names = "default", "sleep";
645 pinctrl-0 = <&blsp2_i2c2_default>;
646 pinctrl-1 = <&blsp2_i2c2_sleep>;
647 #address-cells = <1>;
648 #size-cells = <0>;
653 compatible = "qcom,i2c-qup-v2.1.1";
654 reg = <0xf9967000 0x1000>;
657 clock-names = "core", "iface";
659 dma-names = "tx", "rx";
660 pinctrl-names = "default", "sleep";
661 pinctrl-0 = <&blsp2_i2c5_default>;
662 pinctrl-1 = <&blsp2_i2c5_sleep>;
663 #address-cells = <1>;
664 #size-cells = <0>;
669 compatible = "qcom,i2c-qup-v2.1.1";
670 reg = <0xf9968000 0x1000>;
673 clock-names = "core", "iface";
674 pinctrl-names = "default", "sleep";
675 pinctrl-0 = <&blsp2_i2c6_default>;
676 pinctrl-1 = <&blsp2_i2c6_sleep>;
677 #address-cells = <1>;
678 #size-cells = <0>;
682 compatible = "qcom,ci-hdrc";
683 reg = <0xf9a55000 0x200>,
688 clock-names = "iface", "core";
689 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
690 assigned-clock-rates = <75000000>;
692 reset-names = "core";
695 ahb-burst-config = <0>;
696 phy-names = "usb-phy";
698 #reset-cells = <1>;
701 usb_hs1_phy: phy-0 {
702 compatible = "qcom,usb-hs-phy-msm8974",
703 "qcom,usb-hs-phy";
704 #phy-cells = <0>;
706 clock-names = "ref", "sleep";
708 reset-names = "phy", "por";
712 usb_hs2_phy: phy-1 {
713 compatible = "qcom,usb-hs-phy-msm8974",
714 "qcom,usb-hs-phy";
715 #phy-cells = <0>;
717 clock-names = "ref", "sleep";
719 reset-names = "phy", "por";
727 reg = <0xf9bff000 0x200>;
729 clock-names = "core";
733 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
734 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
735 reg-names = "ccu", "dxe", "pmu";
737 memory-region = <&wcnss_region>;
739 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
744 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
746 qcom,smem-states = <&wcnss_smp2p_out 0>;
747 qcom,smem-state-names = "stop";
755 clock-names = "xo";
758 smd-edge {
762 qcom,smd-edge = <6>;
766 qcom,smd-channels = "WCNSS_CTRL";
772 compatible = "qcom,wcnss-bt";
776 compatible = "qcom,wcnss-wlan";
780 interrupt-names = "tx", "rx";
782 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
783 qcom,smem-state-names = "tx-enable",
784 "tx-rings-empty";
791 compatible = "qcom,msm8974-rpm-stats";
792 reg = <0xfc190000 0x10000>;
796 compatible = "arm,coresight-tmc", "arm,primecell";
797 reg = <0xfc307000 0x1000>;
800 clock-names = "apb_pclk", "atclk";
802 out-ports {
805 remote-endpoint = <&replicator_in>;
810 in-ports {
813 remote-endpoint = <&merger_out>;
820 compatible = "arm,coresight-tpiu", "arm,primecell";
821 reg = <0xfc318000 0x1000>;
824 clock-names = "apb_pclk", "atclk";
826 in-ports {
829 remote-endpoint = <&replicator_out1>;
836 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
837 reg = <0xfc31a000 0x1000>;
840 clock-names = "apb_pclk", "atclk";
842 in-ports {
843 #address-cells = <1>;
844 #size-cells = <0>;
848 * 0 - not-connected
849 * 1 - connected trought funnel to Multimedia CPU
850 * 2 - connected to Wireless CPU
851 * 3 - not-connected
852 * 4 - not-connected
853 * 6 - not-connected
854 * 7 - connected to STM
857 reg = <5>;
859 remote-endpoint = <&kpss_out>;
864 out-ports {
867 remote-endpoint = <&merger_in1>;
874 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
875 reg = <0xfc31b000 0x1000>;
878 clock-names = "apb_pclk", "atclk";
880 in-ports {
881 #address-cells = <1>;
882 #size-cells = <0>;
886 * 0 - connected trought funnel to Audio, Modem and
888 * 2...7 - not-connected
891 reg = <1>;
893 remote-endpoint = <&funnel1_out>;
898 out-ports {
901 remote-endpoint = <&etf_in>;
908 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
909 reg = <0xfc31c000 0x1000>;
912 clock-names = "apb_pclk", "atclk";
914 out-ports {
915 #address-cells = <1>;
916 #size-cells = <0>;
919 reg = <0>;
921 remote-endpoint = <&etr_in>;
925 reg = <1>;
927 remote-endpoint = <&tpiu_in>;
932 in-ports {
935 remote-endpoint = <&etf_out>;
942 compatible = "arm,coresight-tmc", "arm,primecell";
943 reg = <0xfc322000 0x1000>;
946 clock-names = "apb_pclk", "atclk";
948 in-ports {
951 remote-endpoint = <&replicator_out0>;
958 compatible = "arm,coresight-etm4x", "arm,primecell";
959 reg = <0xfc33c000 0x1000>;
962 clock-names = "apb_pclk", "atclk";
966 out-ports {
969 remote-endpoint = <&kpss_in0>;
976 compatible = "arm,coresight-etm4x", "arm,primecell";
977 reg = <0xfc33d000 0x1000>;
980 clock-names = "apb_pclk", "atclk";
984 out-ports {
987 remote-endpoint = <&kpss_in1>;
994 compatible = "arm,coresight-etm4x", "arm,primecell";
995 reg = <0xfc33e000 0x1000>;
998 clock-names = "apb_pclk", "atclk";
1002 out-ports {
1005 remote-endpoint = <&kpss_in2>;
1012 compatible = "arm,coresight-etm4x", "arm,primecell";
1013 reg = <0xfc33f000 0x1000>;
1016 clock-names = "apb_pclk", "atclk";
1020 out-ports {
1023 remote-endpoint = <&kpss_in3>;
1031 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1032 reg = <0xfc345000 0x1000>;
1035 clock-names = "apb_pclk", "atclk";
1037 in-ports {
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1042 reg = <0>;
1044 remote-endpoint = <&etm0_out>;
1048 reg = <1>;
1050 remote-endpoint = <&etm1_out>;
1054 reg = <2>;
1056 remote-endpoint = <&etm2_out>;
1060 reg = <3>;
1062 remote-endpoint = <&etm3_out>;
1067 out-ports {
1070 remote-endpoint = <&funnel1_in5>;
1077 reg = <0xfc380000 0x6a000>;
1078 compatible = "qcom,msm8974-bimc";
1079 #interconnect-cells = <1>;
1080 clock-names = "bus", "bus_a";
1085 gcc: clock-controller@fc400000 {
1086 compatible = "qcom,gcc-msm8974";
1087 #clock-cells = <1>;
1088 #reset-cells = <1>;
1089 #power-domain-cells = <1>;
1090 reg = <0xfc400000 0x4000>;
1094 clock-names = "xo",
1099 compatible = "qcom,rpm-msg-ram";
1100 reg = <0xfc428000 0x4000>;
1102 #address-cells = <1>;
1103 #size-cells = <1>;
1107 reg = <0x150 0x14>;
1111 reg = <0xb50 0x14>;
1115 reg = <0x1550 0x14>;
1119 reg = <0x1f50 0x14>;
1124 reg = <0xfc460000 0x4000>;
1125 compatible = "qcom,msm8974-snoc";
1126 #interconnect-cells = <1>;
1127 clock-names = "bus", "bus_a";
1133 reg = <0xfc468000 0x4000>;
1134 compatible = "qcom,msm8974-pnoc";
1135 #interconnect-cells = <1>;
1136 clock-names = "bus", "bus_a";
1142 reg = <0xfc470000 0x4000>;
1143 compatible = "qcom,msm8974-ocmemnoc";
1144 #interconnect-cells = <1>;
1145 clock-names = "bus", "bus_a";
1151 reg = <0xfc478000 0x4000>;
1152 compatible = "qcom,msm8974-mmssnoc";
1153 #interconnect-cells = <1>;
1154 clock-names = "bus", "bus_a";
1160 reg = <0xfc480000 0x4000>;
1161 compatible = "qcom,msm8974-cnoc";
1162 #interconnect-cells = <1>;
1163 clock-names = "bus", "bus_a";
1168 tsens: thermal-sensor@fc4a9000 {
1169 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
1170 reg = <0xfc4a9000 0x1000>, /* TM */
1172 nvmem-cells = <&tsens_mode>,
1199 nvmem-cell-names = "mode",
1228 interrupt-names = "uplow";
1229 #thermal-sensor-cells = <1>;
1234 reg = <0xfc4ab000 0x4>;
1238 compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
1239 reg = <0xfc4bc000 0x2100>;
1240 #address-cells = <1>;
1241 #size-cells = <1>;
1244 reg = <0xd0 0x1>;
1248 tsens_s0_p1: s0-p1@d1 {
1249 reg = <0xd1 0x1>;
1253 tsens_s1_p1: s1-p1@d2 {
1254 reg = <0xd1 0x2>;
1258 tsens_s2_p1: s2-p1@d2 {
1259 reg = <0xd2 0x2>;
1263 tsens_s3_p1: s3-p1@d3 {
1264 reg = <0xd3 0x1>;
1268 tsens_s4_p1: s4-p1@d4 {
1269 reg = <0xd4 0x1>;
1273 tsens_s5_p1: s5-p1@d4 {
1274 reg = <0xd4 0x2>;
1278 tsens_s6_p1: s6-p1@d5 {
1279 reg = <0xd5 0x2>;
1283 tsens_s7_p1: s7-p1@d6 {
1284 reg = <0xd6 0x1>;
1288 tsens_s8_p1: s8-p1@d7 {
1289 reg = <0xd7 0x1>;
1294 reg = <0xd7 0x1>;
1298 tsens_s9_p1: s9-p1@d8 {
1299 reg = <0xd8 0x1>;
1303 tsens_s10_p1: s10-p1@d8 {
1304 reg = <0xd8 0x2>;
1309 reg = <0xd9 0x2>;
1313 tsens_s0_p2: s0-p2@da {
1314 reg = <0xda 0x2>;
1318 tsens_s1_p2: s1-p2@db {
1319 reg = <0xdb 0x1>;
1323 tsens_s2_p2: s2-p2@dc {
1324 reg = <0xdc 0x1>;
1328 tsens_s3_p2: s3-p2@dc {
1329 reg = <0xdc 0x2>;
1333 tsens_s4_p2: s4-p2@dd {
1334 reg = <0xdd 0x2>;
1338 tsens_s5_p2: s5-p2@de {
1339 reg = <0xde 0x2>;
1343 tsens_s6_p2: s6-p2@df {
1344 reg = <0xdf 0x1>;
1348 tsens_s7_p2: s7-p2@e0 {
1349 reg = <0xe0 0x1>;
1353 tsens_s8_p2: s8-p2@e0 {
1354 reg = <0xe0 0x2>;
1358 tsens_s9_p2: s9-p2@e1 {
1359 reg = <0xe1 0x2>;
1363 tsens_s10_p2: s10-p2@e2 {
1364 reg = <0xe2 0x2>;
1368 tsens_s5_p2_backup: s5-p2-backup@e3 {
1369 reg = <0xe3 0x2>;
1373 tsens_mode_backup: mode-backup@e3 {
1374 reg = <0xe3 0x1>;
1378 tsens_s6_p2_backup: s6-p2-backup@e4 {
1379 reg = <0xe4 0x1>;
1383 tsens_s7_p2_backup: s7-p2-backup@e4 {
1384 reg = <0xe4 0x2>;
1388 tsens_s8_p2_backup: s8-p2-backup@e5 {
1389 reg = <0xe5 0x2>;
1393 tsens_s9_p2_backup: s9-p2-backup@e6 {
1394 reg = <0xe6 0x2>;
1398 tsens_s10_p2_backup: s10-p2-backup@e7 {
1399 reg = <0xe7 0x1>;
1403 tsens_base1_backup: base1-backup@440 {
1404 reg = <0x440 0x1>;
1408 tsens_s0_p1_backup: s0-p1-backup@441 {
1409 reg = <0x441 0x1>;
1413 tsens_s1_p1_backup: s1-p1-backup@442 {
1414 reg = <0x441 0x2>;
1418 tsens_s2_p1_backup: s2-p1-backup@442 {
1419 reg = <0x442 0x2>;
1423 tsens_s3_p1_backup: s3-p1-backup@443 {
1424 reg = <0x443 0x1>;
1428 tsens_s4_p1_backup: s4-p1-backup@444 {
1429 reg = <0x444 0x1>;
1433 tsens_s5_p1_backup: s5-p1-backup@444 {
1434 reg = <0x444 0x2>;
1438 tsens_s6_p1_backup: s6-p1-backup@445 {
1439 reg = <0x445 0x2>;
1443 tsens_s7_p1_backup: s7-p1-backup@446 {
1444 reg = <0x446 0x1>;
1448 tsens_use_backup: use-backup@447 {
1449 reg = <0x447 0x1>;
1453 tsens_s8_p1_backup: s8-p1-backup@448 {
1454 reg = <0x448 0x1>;
1458 tsens_s9_p1_backup: s9-p1-backup@448 {
1459 reg = <0x448 0x2>;
1463 tsens_s10_p1_backup: s10-p1-backup@449 {
1464 reg = <0x449 0x2>;
1468 tsens_base2_backup: base2-backup@44a {
1469 reg = <0x44a 0x2>;
1473 tsens_s0_p2_backup: s0-p2-backup@44b {
1474 reg = <0x44b 0x3>;
1478 tsens_s1_p2_backup: s1-p2-backup@44c {
1479 reg = <0x44c 0x1>;
1483 tsens_s2_p2_backup: s2-p2-backup@44c {
1484 reg = <0x44c 0x2>;
1488 tsens_s3_p2_backup: s3-p2-backup@44d {
1489 reg = <0x44d 0x2>;
1493 tsens_s4_p2_backup: s4-p2-backup@44e {
1494 reg = <0x44e 0x1>;
1500 compatible = "qcom,spmi-pmic-arb";
1501 reg-names = "core", "intr", "cnfg";
1502 reg = <0xfc4cf000 0x1000>,
1505 interrupt-names = "periph_irq";
1509 #address-cells = <2>;
1510 #size-cells = <0>;
1511 interrupt-controller;
1512 #interrupt-cells = <4>;
1515 bam_dmux_dma: dma-controller@fc834000 {
1516 compatible = "qcom,bam-v1.4.0";
1517 reg = <0xfc834000 0x7000>;
1519 #dma-cells = <1>;
1522 num-channels = <6>;
1523 qcom,num-ees = <1>;
1524 qcom,powered-remotely;
1528 compatible = "qcom,msm8974-mss-pil";
1529 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1530 reg-names = "qdsp6", "rmb";
1532 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1537 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1543 clock-names = "iface", "bus", "mem", "xo";
1546 reset-names = "mss_restart";
1548 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
1550 qcom,smem-states = <&modem_smp2p_out 0>;
1551 qcom,smem-state-names = "stop";
1556 memory-region = <&mba_region>;
1560 memory-region = <&mpss_region>;
1563 bam_dmux: bam-dmux {
1564 compatible = "qcom,bam-dmux";
1566 interrupt-parent = <&modem_smsm>;
1568 interrupt-names = "pc", "pc-ack";
1570 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1571 qcom,smem-state-names = "pc", "pc-ack";
1574 dma-names = "tx", "rx";
1577 smd-edge {
1581 qcom,smd-edge = <0>;
1588 compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon";
1589 reg = <0xfd484000 0x2000>;
1590 #hwlock-cells = <1>;
1593 tcsr: syscon@fd4a0000 { label
1594 compatible = "qcom,tcsr-msm8974", "syscon";
1595 reg = <0xfd4a0000 0x10000>;
1599 compatible = "qcom,msm8974-pinctrl";
1600 reg = <0xfd510000 0x4000>;
1601 gpio-controller;
1602 gpio-ranges = <&tlmm 0 0 146>;
1603 #gpio-cells = <2>;
1604 interrupt-controller;
1605 #interrupt-cells = <2>;
1608 sdc1_off: sdc1-off-state {
1609 clk-pins {
1611 bias-disable;
1612 drive-strength = <2>;
1615 cmd-pins {
1617 bias-pull-up;
1618 drive-strength = <2>;
1621 data-pins {
1623 bias-pull-up;
1624 drive-strength = <2>;
1628 sdc2_off: sdc2-off-state {
1629 clk-pins {
1631 bias-disable;
1632 drive-strength = <2>;
1635 cmd-pins {
1637 bias-pull-up;
1638 drive-strength = <2>;
1641 data-pins {
1643 bias-pull-up;
1644 drive-strength = <2>;
1648 blsp1_uart2_default: blsp1-uart2-default-state {
1649 rx-pins {
1652 drive-strength = <2>;
1653 bias-pull-up;
1656 tx-pins {
1659 drive-strength = <4>;
1660 bias-disable;
1664 blsp2_uart1_default: blsp2-uart1-default-state {
1665 tx-rts-pins {
1668 drive-strength = <2>;
1669 bias-disable;
1672 rx-cts-pins {
1675 drive-strength = <2>;
1676 bias-pull-up;
1680 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
1683 drive-strength = <2>;
1684 bias-pull-down;
1687 blsp2_uart4_default: blsp2-uart4-default-state {
1688 tx-rts-pins {
1691 drive-strength = <2>;
1692 bias-disable;
1695 rx-cts-pins {
1698 drive-strength = <2>;
1699 bias-pull-up;
1703 blsp1_i2c1_default: blsp1-i2c1-default-state {
1706 drive-strength = <2>;
1707 bias-disable;
1710 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state {
1713 drive-strength = <2>;
1714 bias-pull-up;
1717 blsp1_i2c2_default: blsp1-i2c2-default-state {
1720 drive-strength = <2>;
1721 bias-disable;
1724 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
1727 drive-strength = <2>;
1728 bias-pull-up;
1731 blsp1_i2c3_default: blsp1-i2c3-default-state {
1734 drive-strength = <2>;
1735 bias-disable;
1738 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1741 drive-strength = <2>;
1742 bias-pull-up;
1749 blsp1_i2c6_default: blsp1-i2c6-default-state {
1752 drive-strength = <2>;
1753 bias-disable;
1756 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1759 drive-strength = <2>;
1760 bias-pull-up;
1766 blsp2_i2c2_default: blsp2-i2c2-default-state {
1769 drive-strength = <2>;
1770 bias-disable;
1773 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1776 drive-strength = <2>;
1777 bias-pull-up;
1784 blsp2_i2c5_default: blsp2-i2c5-default-state {
1787 drive-strength = <2>;
1788 bias-disable;
1791 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1794 drive-strength = <2>;
1795 bias-pull-up;
1798 blsp2_i2c6_default: blsp2-i2c6-default-state {
1801 drive-strength = <2>;
1802 bias-disable;
1805 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1808 drive-strength = <2>;
1809 bias-pull-up;
1812 cci_default: cci-default-state {
1813 cci_i2c0_default: cci-i2c0-default-pins {
1816 drive-strength = <2>;
1817 bias-disable;
1820 cci_i2c1_default: cci-i2c1-default-pins {
1823 drive-strength = <2>;
1824 bias-disable;
1828 cci_sleep: cci-sleep-state {
1829 cci_i2c0_sleep: cci-i2c0-sleep-pins {
1832 drive-strength = <2>;
1833 bias-disable;
1836 cci_i2c1_sleep: cci-i2c1-sleep-pins {
1839 drive-strength = <2>;
1840 bias-disable;
1844 spi8_default: spi8_default-state {
1845 mosi-pins {
1849 miso-pins {
1853 cs-pins {
1857 clk-pins {
1864 mmcc: clock-controller@fd8c0000 {
1865 compatible = "qcom,mmcc-msm8974";
1866 #clock-cells = <1>;
1867 #reset-cells = <1>;
1868 #power-domain-cells = <1>;
1869 reg = <0xfd8c0000 0x6000>;
1882 clock-names = "xo",
1896 mdss: display-subsystem@fd900000 {
1898 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1899 reg-names = "mdss_phys", "vbif_phys";
1901 power-domains = <&mmcc MDSS_GDSC>;
1906 clock-names = "iface", "bus", "vsync";
1910 interrupt-controller;
1911 #interrupt-cells = <1>;
1915 #address-cells = <1>;
1916 #size-cells = <1>;
1919 mdp: display-controller@fd900000 {
1920 compatible = "qcom,msm8974-mdp5", "qcom,mdp5";
1921 reg = <0xfd900100 0x22000>;
1922 reg-names = "mdp_phys";
1924 interrupt-parent = <&mdss>;
1931 clock-names = "iface", "bus", "core", "vsync";
1934 interconnect-names = "mdp0-mem";
1937 #address-cells = <1>;
1938 #size-cells = <0>;
1941 reg = <0>;
1943 remote-endpoint = <&mdss_dsi0_in>;
1948 reg = <1>;
1950 remote-endpoint = <&mdss_dsi1_in>;
1957 compatible = "qcom,msm8974-dsi-ctrl",
1958 "qcom,mdss-dsi-ctrl";
1959 reg = <0xfd922800 0x1f8>;
1960 reg-names = "dsi_ctrl";
1962 interrupt-parent = <&mdss>;
1965 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1967 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1977 clock-names = "mdp_core",
1989 #address-cells = <1>;
1990 #size-cells = <0>;
1993 #address-cells = <1>;
1994 #size-cells = <0>;
1997 reg = <0>;
1999 remote-endpoint = <&mdp5_intf1_out>;
2004 reg = <1>;
2012 compatible = "qcom,dsi-phy-28nm-hpm";
2013 reg = <0xfd922a00 0xd4>,
2016 reg-names = "dsi_pll",
2020 #clock-cells = <1>;
2021 #phy-cells = <0>;
2024 clock-names = "iface", "ref";
2030 compatible = "qcom,msm8974-dsi-ctrl",
2031 "qcom,mdss-dsi-ctrl";
2032 reg = <0xfd922e00 0x1f8>;
2033 reg-names = "dsi_ctrl";
2035 interrupt-parent = <&mdss>;
2038 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2040 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
2050 clock-names = "mdp_core",
2062 #address-cells = <1>;
2063 #size-cells = <0>;
2066 #address-cells = <1>;
2067 #size-cells = <0>;
2070 reg = <0>;
2072 remote-endpoint = <&mdp5_intf2_out>;
2077 reg = <1>;
2085 compatible = "qcom,dsi-phy-28nm-hpm";
2086 reg = <0xfd923000 0xd4>,
2089 reg-names = "dsi_pll",
2093 #clock-cells = <1>;
2094 #phy-cells = <0>;
2097 clock-names = "iface", "ref";
2104 compatible = "qcom,msm8974-cci";
2105 #address-cells = <1>;
2106 #size-cells = <0>;
2107 reg = <0xfda0c000 0x1000>;
2112 clock-names = "camss_top_ahb",
2116 pinctrl-names = "default", "sleep";
2117 pinctrl-0 = <&cci_default>;
2118 pinctrl-1 = <&cci_sleep>;
2122 cci_i2c0: i2c-bus@0 {
2123 reg = <0>;
2124 clock-frequency = <100000>;
2125 #address-cells = <1>;
2126 #size-cells = <0>;
2129 cci_i2c1: i2c-bus@1 {
2130 reg = <1>;
2131 clock-frequency = <100000>;
2132 #address-cells = <1>;
2133 #size-cells = <0>;
2138 compatible = "qcom,adreno-330.1", "qcom,adreno";
2139 reg = <0xfdb00000 0x10000>;
2140 reg-names = "kgsl_3d0_reg_memory";
2143 interrupt-names = "kgsl_3d0_irq";
2148 clock-names = "core", "iface", "mem_iface";
2151 power-domains = <&mmcc OXILICX_GDSC>;
2152 operating-points-v2 = <&gpu_opp_table>;
2156 interconnect-names = "gfx-mem", "ocmem";
2162 gpu_opp_table: opp-table {
2163 compatible = "operating-points-v2";
2165 opp-320000000 {
2166 opp-hz = /bits/ 64 <320000000>;
2169 opp-200000000 {
2170 opp-hz = /bits/ 64 <200000000>;
2173 opp-27000000 {
2174 opp-hz = /bits/ 64 <27000000>;
2180 compatible = "qcom,msm8974-ocmem";
2181 reg = <0xfdd00000 0x2000>,
2183 reg-names = "ctrl", "mem";
2187 clock-names = "core", "iface";
2189 #address-cells = <1>;
2190 #size-cells = <1>;
2192 gmu_sram: gmu-sram@0 {
2193 reg = <0x0 0x100000>;
2198 compatible = "qcom,msm8974-adsp-pil";
2199 reg = <0xfe200000 0x100>;
2201 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2206 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2209 clock-names = "xo";
2211 memory-region = <&adsp_region>;
2213 qcom,smem-states = <&adsp_smp2p_out 0>;
2214 qcom,smem-state-names = "stop";
2218 smd-edge {
2222 qcom,smd-edge = <1>;
2228 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
2229 reg = <0xfe805000 0x1000>;
2231 reboot-mode {
2232 compatible = "syscon-reboot-mode";
2238 thermal-zones {
2239 cpu0-thermal {
2240 polling-delay-passive = <250>;
2241 polling-delay = <1000>;
2243 thermal-sensors = <&tsens 5>;
2259 cpu1-thermal {
2260 polling-delay-passive = <250>;
2261 polling-delay = <1000>;
2263 thermal-sensors = <&tsens 6>;
2279 cpu2-thermal {
2280 polling-delay-passive = <250>;
2281 polling-delay = <1000>;
2283 thermal-sensors = <&tsens 7>;
2299 cpu3-thermal {
2300 polling-delay-passive = <250>;
2301 polling-delay = <1000>;
2303 thermal-sensors = <&tsens 8>;
2319 q6-dsp-thermal {
2320 polling-delay-passive = <250>;
2321 polling-delay = <1000>;
2323 thermal-sensors = <&tsens 1>;
2326 q6_dsp_alert0: trip-point0 {
2334 modemtx-thermal {
2335 polling-delay-passive = <250>;
2336 polling-delay = <1000>;
2338 thermal-sensors = <&tsens 2>;
2341 modemtx_alert0: trip-point0 {
2349 video-thermal {
2350 polling-delay-passive = <250>;
2351 polling-delay = <1000>;
2353 thermal-sensors = <&tsens 3>;
2356 video_alert0: trip-point0 {
2364 wlan-thermal {
2365 polling-delay-passive = <250>;
2366 polling-delay = <1000>;
2368 thermal-sensors = <&tsens 4>;
2371 wlan_alert0: trip-point0 {
2379 gpu-top-thermal {
2380 polling-delay-passive = <250>;
2381 polling-delay = <1000>;
2383 thermal-sensors = <&tsens 9>;
2386 gpu1_alert0: trip-point0 {
2394 gpu-bottom-thermal {
2395 polling-delay-passive = <250>;
2396 polling-delay = <1000>;
2398 thermal-sensors = <&tsens 10>;
2401 gpu2_alert0: trip-point0 {
2411 compatible = "arm,armv7-timer";
2416 clock-frequency = <19200000>;