Lines Matching +full:0 +full:xfc4cf000
22 #clock-cells = <0>;
28 #clock-cells = <0>;
35 #size-cells = <0>;
38 cpu0: cpu@0 {
42 reg = <0>;
108 memory@0 {
110 reg = <0x0 0x0>;
135 mboxes = <&apcs 0>;
158 reg = <0x08000000 0x5100000>;
163 reg = <0x0d100000 0x100000>;
168 reg = <0x0d200000 0xa00000>;
173 reg = <0x0dc00000 0x1900000>;
178 reg = <0x0f500000 0x500000>;
183 reg = <0xfa00000 0x200000>;
188 reg = <0x0fc00000 0x160000>;
193 reg = <0x0fd60000 0x20000>;
199 reg = <0x0fd80000 0x180000>;
224 qcom,local-pid = <0>;
249 qcom,local-pid = <0>;
274 qcom,local-pid = <0>;
295 #size-cells = <0>;
297 mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>;
299 apps_smsm: apps@0 {
300 reg = <0>;
340 reg = <0xf9000000 0x1000>,
341 <0xf9002000 0x1000>;
347 reg = <0xf9011000 0x1000>;
353 reg = <0xf9012000 0x1000>;
358 reg = <0xf9017000 0x1000>;
369 reg = <0xf9020000 0x1000>;
373 frame-number = <0>;
376 reg = <0xf9021000 0x1000>,
377 <0xf9022000 0x1000>;
383 reg = <0xf9023000 0x1000>;
390 reg = <0xf9024000 0x1000>;
397 reg = <0xf9025000 0x1000>;
404 reg = <0xf9026000 0x1000>;
411 reg = <0xf9027000 0x1000>;
418 reg = <0xf9028000 0x1000>;
425 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
430 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
435 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
440 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
445 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
450 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
455 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
460 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
465 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
482 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
494 #size-cells = <0>;
501 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
513 #size-cells = <0>;
520 reg = <0xf991d000 0x1000>;
529 reg = <0xf991e000 0x1000>;
534 pinctrl-0 = <&blsp1_uart2_default>;
541 reg = <0xf9923000 0x1000>;
546 pinctrl-0 = <&blsp1_i2c1_default>;
549 #size-cells = <0>;
555 reg = <0xf9924000 0x1000>;
560 pinctrl-0 = <&blsp1_i2c2_default>;
563 #size-cells = <0>;
569 reg = <0xf9925000 0x1000>;
574 pinctrl-0 = <&blsp1_i2c3_default>;
577 #size-cells = <0>;
583 reg = <0xf9928000 0x1000>;
588 pinctrl-0 = <&blsp1_i2c6_default>;
591 #size-cells = <0>;
596 reg = <0xf9944000 0x19000>;
601 qcom,ee = <0>;
606 reg = <0xf995d000 0x1000>;
611 pinctrl-0 = <&blsp2_uart1_default>;
618 reg = <0xf995e000 0x1000>;
627 reg = <0xf9960000 0x1000>;
632 pinctrl-0 = <&blsp2_uart4_default>;
639 reg = <0xf9964000 0x1000>;
644 pinctrl-0 = <&blsp2_i2c2_default>;
647 #size-cells = <0>;
653 reg = <0xf9967000 0x1000>;
660 pinctrl-0 = <&blsp2_i2c5_default>;
663 #size-cells = <0>;
669 reg = <0xf9968000 0x1000>;
674 pinctrl-0 = <&blsp2_i2c6_default>;
677 #size-cells = <0>;
682 reg = <0xf9a55000 0x200>,
683 <0xf9a55200 0x200>;
694 ahb-burst-config = <0>;
700 usb_hs1_phy: phy-0 {
703 #phy-cells = <0>;
706 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
714 #phy-cells = <0>;
726 reg = <0xf9bff000 0x200>;
733 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
739 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
745 qcom,smem-states = <&wcnss_smp2p_out 0>;
791 reg = <0xfc190000 0x10000>;
796 reg = <0xfc307000 0x1000>;
820 reg = <0xfc318000 0x1000>;
836 reg = <0xfc31a000 0x1000>;
843 #size-cells = <0>;
847 * 0 - not-connected
874 reg = <0xfc31b000 0x1000>;
881 #size-cells = <0>;
885 * 0 - connected trought funnel to Audio, Modem and
908 reg = <0xfc31c000 0x1000>;
915 #size-cells = <0>;
917 port@0 {
918 reg = <0>;
942 reg = <0xfc322000 0x1000>;
958 reg = <0xfc33c000 0x1000>;
976 reg = <0xfc33d000 0x1000>;
994 reg = <0xfc33e000 0x1000>;
1012 reg = <0xfc33f000 0x1000>;
1031 reg = <0xfc345000 0x1000>;
1038 #size-cells = <0>;
1040 port@0 {
1041 reg = <0>;
1076 reg = <0xfc380000 0x6a000>;
1089 reg = <0xfc400000 0x4000>;
1099 reg = <0xfc428000 0x4000>;
1103 ranges = <0 0xfc428000 0x4000>;
1106 reg = <0x150 0x14>;
1110 reg = <0xb50 0x14>;
1114 reg = <0x1550 0x14>;
1118 reg = <0x1f50 0x14>;
1123 reg = <0xfc460000 0x4000>;
1132 reg = <0xfc468000 0x4000>;
1141 reg = <0xfc470000 0x4000>;
1150 reg = <0xfc478000 0x4000>;
1159 reg = <0xfc480000 0x4000>;
1169 reg = <0xfc4a9000 0x1000>, /* TM */
1170 <0xfc4a8000 0x1000>; /* SROT */
1233 reg = <0xfc4ab000 0x4>;
1238 reg = <0xfc4bc000 0x2100>;
1243 reg = <0xd0 0x1>;
1244 bits = <0 8>;
1248 reg = <0xd1 0x1>;
1249 bits = <0 6>;
1253 reg = <0xd1 0x2>;
1258 reg = <0xd2 0x2>;
1263 reg = <0xd3 0x1>;
1268 reg = <0xd4 0x1>;
1269 bits = <0 6>;
1273 reg = <0xd4 0x2>;
1278 reg = <0xd5 0x2>;
1283 reg = <0xd6 0x1>;
1288 reg = <0xd7 0x1>;
1289 bits = <0 6>;
1293 reg = <0xd7 0x1>;
1298 reg = <0xd8 0x1>;
1299 bits = <0 6>;
1303 reg = <0xd8 0x2>;
1308 reg = <0xd9 0x2>;
1313 reg = <0xda 0x2>;
1318 reg = <0xdb 0x1>;
1323 reg = <0xdc 0x1>;
1324 bits = <0 6>;
1328 reg = <0xdc 0x2>;
1333 reg = <0xdd 0x2>;
1338 reg = <0xde 0x2>;
1343 reg = <0xdf 0x1>;
1344 bits = <0 6>;
1348 reg = <0xe0 0x1>;
1349 bits = <0 6>;
1353 reg = <0xe0 0x2>;
1358 reg = <0xe1 0x2>;
1363 reg = <0xe2 0x2>;
1368 reg = <0xe3 0x2>;
1369 bits = <0 6>;
1373 reg = <0xe3 0x1>;
1378 reg = <0xe4 0x1>;
1379 bits = <0 6>;
1383 reg = <0xe4 0x2>;
1388 reg = <0xe5 0x2>;
1393 reg = <0xe6 0x2>;
1398 reg = <0xe7 0x1>;
1399 bits = <0 6>;
1403 reg = <0x440 0x1>;
1404 bits = <0 8>;
1408 reg = <0x441 0x1>;
1409 bits = <0 6>;
1413 reg = <0x441 0x2>;
1418 reg = <0x442 0x2>;
1423 reg = <0x443 0x1>;
1428 reg = <0x444 0x1>;
1429 bits = <0 6>;
1433 reg = <0x444 0x2>;
1438 reg = <0x445 0x2>;
1443 reg = <0x446 0x1>;
1448 reg = <0x447 0x1>;
1453 reg = <0x448 0x1>;
1454 bits = <0 6>;
1458 reg = <0x448 0x2>;
1463 reg = <0x449 0x2>;
1468 reg = <0x44a 0x2>;
1473 reg = <0x44b 0x3>;
1478 reg = <0x44c 0x1>;
1479 bits = <0 6>;
1483 reg = <0x44c 0x2>;
1488 reg = <0x44d 0x2>;
1493 reg = <0x44e 0x1>;
1501 reg = <0xfc4cf000 0x1000>,
1502 <0xfc4cb000 0x1000>,
1503 <0xfc4ca000 0x1000>;
1506 qcom,ee = <0>;
1507 qcom,channel = <0>;
1509 #size-cells = <0>;
1516 reg = <0xfc834000 0x7000>;
1519 qcom,ee = <0>;
1528 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1532 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1547 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
1549 qcom,smem-states = <&modem_smp2p_out 0>;
1580 qcom,smd-edge = <0>;
1588 reg = <0xfd484000 0x2000>;
1594 reg = <0xfd4a0000 0x10000>;
1599 reg = <0xfd510000 0x4000>;
1601 gpio-ranges = <&tlmm 0 0 146>;
1868 reg = <0xfd8c0000 0x6000>;
1875 <&mdss_dsi0_phy 0>,
1877 <&mdss_dsi1_phy 0>,
1878 <0>,
1879 <0>,
1880 <0>;
1897 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1920 reg = <0xfd900100 0x22000>;
1924 interrupts = <0>;
1937 #size-cells = <0>;
1939 port@0 {
1940 reg = <0>;
1958 reg = <0xfd922800 0x1f8>;
1965 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1987 #size-cells = <0>;
1991 #size-cells = <0>;
1993 port@0 {
1994 reg = <0>;
2010 reg = <0xfd922a00 0xd4>,
2011 <0xfd922b00 0x280>,
2012 <0xfd922d80 0x30>;
2018 #phy-cells = <0>;
2029 reg = <0xfd922e00 0x1f8>;
2036 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2058 #size-cells = <0>;
2062 #size-cells = <0>;
2064 port@0 {
2065 reg = <0>;
2081 reg = <0xfd923000 0xd4>,
2082 <0xfd923100 0x280>,
2083 <0xfd923380 0x30>;
2089 #phy-cells = <0>;
2101 #size-cells = <0>;
2102 reg = <0xfda0c000 0x1000>;
2112 pinctrl-0 = <&cci_default>;
2117 cci_i2c0: i2c-bus@0 {
2118 reg = <0>;
2121 #size-cells = <0>;
2128 #size-cells = <0>;
2134 reg = <0xfdb00000 0x10000>;
2153 // iommus = <&gpu_iommu 0>;
2176 reg = <0xfdd00000 0x2000>,
2177 <0xfec00000 0x180000>;
2179 ranges = <0 0xfec00000 0x180000>;
2187 gmu_sram: gmu-sram@0 {
2188 reg = <0x0 0x100000>;
2194 reg = <0xfe200000 0x100>;
2197 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2208 qcom,smem-states = <&adsp_smp2p_out 0>;
2224 reg = <0xfe805000 0x1000>;
2228 offset = <0x65c>;