Lines Matching +full:cap +full:- +full:mmc +full:- +full:highspeed
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 enable-method = "qcom,gcc-msm8660";
25 next-level-cache = <&L2>;
30 enable-method = "qcom,gcc-msm8660";
33 next-level-cache = <&L2>;
36 L2: l2-cache {
38 cache-level = <2>;
39 cache-unified;
48 cpu-pmu {
49 compatible = "qcom,scorpion-mp-pmu";
54 cxo_board: cxo-board-clk {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <19200000>;
58 clock-output-names = "cxo_board";
61 pxo_board: pxo-board-clk {
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <27000000>;
65 clock-output-names = "pxo_board";
68 sleep-clk {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <32768>;
72 clock-output-names = "sleep_clk";
77 #address-cells = <1>;
78 #size-cells = <1>;
80 compatible = "simple-bus";
82 intc: interrupt-controller@2080000 {
83 compatible = "qcom,msm-8660-qgic";
84 interrupt-controller;
85 #interrupt-cells = <3>;
91 compatible = "qcom,scss-timer", "qcom,msm-timer";
96 clock-frequency = <27000000>;
97 cpu-offset = <0x40000>;
101 compatible = "qcom,msm8660-pinctrl";
104 gpio-controller;
105 gpio-ranges = <&tlmm 0 0 173>;
106 #gpio-cells = <2>;
108 interrupt-controller;
109 #interrupt-cells = <2>;
113 gcc: clock-controller@900000 {
114 compatible = "qcom,gcc-msm8660";
115 #clock-cells = <1>;
116 #reset-cells = <1>;
119 clock-names = "pxo", "cxo";
123 compatible = "qcom,gsbi-v1.0.0";
124 cell-index = <12>;
127 clock-names = "iface";
128 #address-cells = <1>;
129 #size-cells = <1>;
132 syscon-tcsr = <&tcsr>;
137 compatible = "qcom,spi-qup-v1.1.1";
141 clock-names = "core", "iface";
142 #address-cells = <1>;
143 #size-cells = <0>;
149 compatible = "qcom,gsbi-v1.0.0";
150 cell-index = <12>;
153 clock-names = "iface";
154 #address-cells = <1>;
155 #size-cells = <1>;
158 syscon-tcsr = <&tcsr>;
162 compatible = "qcom,i2c-qup-v1.1.1";
166 clock-names = "core", "iface";
167 #address-cells = <1>;
168 #size-cells = <0>;
174 compatible = "qcom,gsbi-v1.0.0";
175 cell-index = <12>;
178 clock-names = "iface";
179 #address-cells = <1>;
180 #size-cells = <1>;
184 syscon-tcsr = <&tcsr>;
187 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
192 clock-names = "core", "iface";
197 compatible = "qcom,i2c-qup-v1.1.1";
201 clock-names = "core", "iface";
202 #address-cells = <1>;
203 #size-cells = <0>;
209 compatible = "qcom,gsbi-v1.0.0";
210 cell-index = <12>;
213 clock-names = "iface";
214 #address-cells = <1>;
215 #size-cells = <1>;
219 syscon-tcsr = <&tcsr>;
222 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
227 clock-names = "core", "iface";
232 compatible = "qcom,i2c-qup-v1.1.1";
236 clock-names = "core", "iface";
237 #address-cells = <1>;
238 #size-cells = <0>;
244 compatible = "qcom,gsbi-v1.0.0";
245 cell-index = <12>;
248 clock-names = "iface";
249 #address-cells = <1>;
250 #size-cells = <1>;
253 syscon-tcsr = <&tcsr>;
257 compatible = "qcom,i2c-qup-v1.1.1";
261 clock-names = "core", "iface";
262 #address-cells = <1>;
263 #size-cells = <0>;
269 compatible = "qcom,gsbi-v1.0.0";
270 cell-index = <12>;
273 clock-names = "iface";
274 #address-cells = <1>;
275 #size-cells = <1>;
278 syscon-tcsr = <&tcsr>;
281 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
286 clock-names = "core", "iface";
291 compatible = "qcom,i2c-qup-v1.1.1";
295 clock-names = "core", "iface";
296 #address-cells = <1>;
297 #size-cells = <0>;
302 ebi2: external-bus@1a100000 {
303 compatible = "qcom,msm8660-ebi2";
304 #address-cells = <2>;
305 #size-cells = <1>;
313 reg-names = "ebi2", "xmem";
315 clock-names = "ebi2x", "ebi2";
322 qcom,controller-type = "pmic-arbiter";
325 l2cc: clock-controller@2082000 {
326 compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon";
331 compatible = "qcom,rpm-msm8660";
338 interrupt-names = "ack", "err", "wakeup";
340 clock-names = "ram";
342 rpmcc: clock-controller {
343 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
344 #clock-cells = <1>;
346 clock-names = "pxo";
351 compatible = "simple-bus";
352 #address-cells = <1>;
353 #size-cells = <1>;
355 sdcc1: mmc@12400000 {
358 arm,primecell-periphid = <0x00051180>;
362 clock-names = "mclk", "apb_pclk";
363 bus-width = <8>;
364 max-frequency = <48000000>;
365 non-removable;
366 cap-sd-highspeed;
367 cap-mmc-highspeed;
370 sdcc2: mmc@12140000 {
373 arm,primecell-periphid = <0x00051180>;
377 clock-names = "mclk", "apb_pclk";
378 bus-width = <8>;
379 max-frequency = <48000000>;
380 cap-sd-highspeed;
381 cap-mmc-highspeed;
384 sdcc3: mmc@12180000 {
386 arm,primecell-periphid = <0x00051180>;
391 clock-names = "mclk", "apb_pclk";
392 bus-width = <4>;
393 cap-sd-highspeed;
394 cap-mmc-highspeed;
395 max-frequency = <48000000>;
396 no-1-8-v;
399 sdcc4: mmc@121c0000 {
401 arm,primecell-periphid = <0x00051180>;
406 clock-names = "mclk", "apb_pclk";
407 bus-width = <4>;
408 max-frequency = <48000000>;
409 cap-sd-highspeed;
410 cap-mmc-highspeed;
413 sdcc5: mmc@12200000 {
415 arm,primecell-periphid = <0x00051180>;
420 clock-names = "mclk", "apb_pclk";
421 bus-width = <4>;
422 cap-sd-highspeed;
423 cap-mmc-highspeed;
424 max-frequency = <48000000>;
429 compatible = "qcom,tcsr-msm8660", "syscon";