Lines Matching refs:gcc

10 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
15 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
105 			clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
347 			clocks = <&a7pll>, <&gcc GPLL0_VOTE>;
531 			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
532 				 <&gcc GCC_SDCC1_APPS_CLK>,
547 			clocks = <&gcc GCC_SDCC3_AHB_CLK>,
548 				 <&gcc GCC_SDCC3_APPS_CLK>,
563 			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
564 				 <&gcc GCC_SDCC2_APPS_CLK>,
576 			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
585 			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
586 				 <&gcc GCC_BLSP1_AHB_CLK>;
596 			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
605 			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
614 			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
627 			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
640 			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
653 			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
666 			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
679 			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
680 				 <&gcc GCC_BLSP1_AHB_CLK>;
695 			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
696 				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
698 			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
700 			resets = <&gcc GCC_USB_HS_BCR>;
719 						 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
721 					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
732 			clocks = <&gcc GCC_PRNG_AHB_CLK>;
741 		gcc: clock-controller@fc400000 {  label
742 			compatible = "qcom,gcc-msm8226";
950 			clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
951 				 <&gcc GCC_MSS_CFG_AHB_CLK>,
952 				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
959 			resets = <&gcc GCC_MSS_RESTART>;
1138 				 <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
1139 				 <&gcc GPLL0_VOTE>,
1140 				 <&gcc GPLL1_VOTE>,