Lines Matching +full:smp2p +full:- +full:mpss
1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
11 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
12 #include <dt-bindings/clock/qcom,rpmcc.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
16 #include <dt-bindings/thermal/thermal.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&intc>;
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <19200000>;
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <32768>;
40 #address-cells = <1>;
41 #size-cells = <0>;
44 compatible = "arm,cortex-a7";
45 enable-method = "qcom,msm8226-smp";
48 next-level-cache = <&l2>;
50 operating-points-v2 = <&cpu_opp_table>;
53 #cooling-cells = <2>;
57 compatible = "arm,cortex-a7";
58 enable-method = "qcom,msm8226-smp";
61 next-level-cache = <&l2>;
63 operating-points-v2 = <&cpu_opp_table>;
66 #cooling-cells = <2>;
70 compatible = "arm,cortex-a7";
71 enable-method = "qcom,msm8226-smp";
74 next-level-cache = <&l2>;
76 operating-points-v2 = <&cpu_opp_table>;
79 #cooling-cells = <2>;
83 compatible = "arm,cortex-a7";
84 enable-method = "qcom,msm8226-smp";
87 next-level-cache = <&l2>;
89 operating-points-v2 = <&cpu_opp_table>;
92 #cooling-cells = <2>;
95 l2: l2-cache {
97 cache-level = <2>;
98 cache-unified;
104 compatible = "qcom,scm-msm8226", "qcom,scm";
106 clock-names = "core", "bus", "iface";
115 cpu_opp_table: opp-table-cpu {
116 compatible = "operating-points-v2";
117 opp-shared;
119 opp-300000000 {
120 opp-hz = /bits/ 64 <300000000>;
123 opp-384000000 {
124 opp-hz = /bits/ 64 <384000000>;
127 opp-600000000 {
128 opp-hz = /bits/ 64 <600000000>;
131 opp-787200000 {
132 opp-hz = /bits/ 64 <787200000>;
139 compatible = "arm,cortex-a7-pmu";
145 compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc";
147 master-stats {
148 compatible = "qcom,rpm-master-stats";
149 qcom,rpm-msg-ram = <&apss_master_stats>,
153 qcom,master-names = "APSS",
154 "MPSS",
159 smd-edge {
162 qcom,smd-edge = <15>;
164 rpm_requests: rpm-requests {
165 compatible = "qcom,rpm-msm8226", "qcom,smd-rpm";
166 qcom,smd-channels = "rpm_requests";
168 rpmcc: clock-controller {
169 compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc";
170 #clock-cells = <1>;
172 clock-names = "xo";
175 rpmpd: power-controller {
176 compatible = "qcom,msm8226-rpmpd";
177 #power-domain-cells = <1>;
178 operating-points-v2 = <&rpmpd_opp_table>;
180 rpmpd_opp_table: opp-table {
181 compatible = "operating-points-v2";
184 opp-level = <1>;
187 opp-level = <2>;
190 opp-level = <3>;
193 opp-level = <4>;
196 opp-level = <5>;
199 opp-level = <6>;
207 reserved-memory {
208 #address-cells = <1>;
209 #size-cells = <1>;
214 no-map;
217 mpss_region: mpss@8000000 {
219 no-map;
225 no-map;
231 no-map;
238 memory-region = <&smem_region>;
239 qcom,rpm-msg-ram = <&rpm_msg_ram>;
244 smp2p-adsp {
245 compatible = "qcom,smp2p";
248 interrupt-parent = <&intc>;
253 qcom,local-pid = <0>;
254 qcom,remote-pid = <2>;
256 adsp_smp2p_out: master-kernel {
257 qcom,entry-name = "master-kernel";
258 #qcom,smem-state-cells = <1>;
261 adsp_smp2p_in: slave-kernel {
262 qcom,entry-name = "slave-kernel";
264 interrupt-controller;
265 #interrupt-cells = <2>;
269 smp2p-modem {
270 compatible = "qcom,smp2p";
273 interrupt-parent = <&intc>;
278 qcom,local-pid = <0>;
279 qcom,remote-pid = <1>;
281 modem_smp2p_out: master-kernel {
282 qcom,entry-name = "master-kernel";
283 #qcom,smem-state-cells = <1>;
286 modem_smp2p_in: slave-kernel {
287 qcom,entry-name = "slave-kernel";
289 interrupt-controller;
290 #interrupt-cells = <2>;
296 #address-cells = <1>;
297 #size-cells = <0>;
303 #qcom,smem-state-cells = <1>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
323 interrupt-controller;
324 #interrupt-cells = <2>;
329 compatible = "simple-bus";
330 #address-cells = <1>;
331 #size-cells = <1>;
334 intc: interrupt-controller@f9000000 {
335 compatible = "qcom,msm-qgic2";
338 interrupt-controller;
339 #interrupt-cells = <3>;
343 compatible = "qcom,msm8226-apcs-kpss-global",
344 "qcom,msm8916-apcs-kpss-global", "syscon";
346 #mbox-cells = <1>;
348 clock-names = "pll", "aux";
349 #clock-cells = <0>;
353 compatible = "qcom,msm8226-a7pll";
355 #clock-cells = <0>;
357 clock-names = "xo";
358 operating-points-v2 = <&a7pll_opp_table>;
360 a7pll_opp_table: opp-table {
361 compatible = "operating-points-v2";
363 opp-768000000 {
364 opp-hz = /bits/ 64 <768000000>;
367 opp-787200000 {
368 opp-hz = /bits/ 64 <787200000>;
371 opp-998400000 {
372 opp-hz = /bits/ 64 <998400000>;
375 opp-1094400000 {
376 opp-hz = /bits/ 64 <1094400000>;
379 opp-1190400000 {
380 opp-hz = /bits/ 64 <1190400000>;
383 opp-1305600000 {
384 opp-hz = /bits/ 64 <1305600000>;
387 opp-1344000000 {
388 opp-hz = /bits/ 64 <1344000000>;
391 opp-1401600000 {
392 opp-hz = /bits/ 64 <1401600000>;
395 opp-1497600000 {
396 opp-hz = /bits/ 64 <1497600000>;
399 opp-1593600000 {
400 opp-hz = /bits/ 64 <1593600000>;
403 opp-1689600000 {
404 opp-hz = /bits/ 64 <1689600000>;
407 opp-1785600000 {
408 opp-hz = /bits/ 64 <1785600000>;
413 saw_l2: power-manager@f9012000 {
414 compatible = "qcom,msm8226-saw2-v2.1-l2", "qcom,saw2";
419 compatible = "qcom,apss-wdt-msm8226", "qcom,kpss-wdt";
427 compatible = "arm,armv7-timer-mem";
429 #address-cells = <1>;
430 #size-cells = <1>;
434 frame-number = <0>;
442 frame-number = <1>;
449 frame-number = <2>;
456 frame-number = <3>;
463 frame-number = <4>;
470 frame-number = <5>;
477 frame-number = <6>;
484 acc0: power-manager@f9088000 {
485 compatible = "qcom,kpss-acc-v2";
489 saw0: power-manager@f9089000 {
490 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
494 acc1: power-manager@f9098000 {
495 compatible = "qcom,kpss-acc-v2";
499 saw1: power-manager@f9099000 {
500 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
504 acc2: power-manager@f90a8000 {
505 compatible = "qcom,kpss-acc-v2";
509 saw2: power-manager@f90a9000 {
510 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
514 acc3: power-manager@f90b8000 {
515 compatible = "qcom,kpss-acc-v2";
519 saw3: power-manager@f90b9000 {
520 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
525 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
527 reg-names = "hc", "core";
530 interrupt-names = "hc_irq", "pwr_irq";
534 clock-names = "iface", "core", "xo";
535 pinctrl-names = "default";
536 pinctrl-0 = <&sdhc1_default_state>;
541 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
543 reg-names = "hc", "core";
546 interrupt-names = "hc_irq", "pwr_irq";
550 clock-names = "iface", "core", "xo";
551 pinctrl-names = "default";
552 pinctrl-0 = <&sdhc3_default_state>;
557 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
559 reg-names = "hc", "core";
562 interrupt-names = "hc_irq", "pwr_irq";
566 clock-names = "iface", "core", "xo";
567 pinctrl-names = "default";
568 pinctrl-0 = <&sdhc2_default_state>;
573 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
577 clock-names = "core", "iface";
582 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
587 clock-names = "core",
593 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
597 clock-names = "core", "iface";
602 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
606 clock-names = "core", "iface";
611 compatible = "qcom,i2c-qup-v2.1.1";
615 clock-names = "core", "iface";
616 pinctrl-names = "default";
617 pinctrl-0 = <&blsp1_i2c1_pins>;
618 #address-cells = <1>;
619 #size-cells = <0>;
624 compatible = "qcom,i2c-qup-v2.1.1";
628 clock-names = "core", "iface";
629 pinctrl-names = "default";
630 pinctrl-0 = <&blsp1_i2c2_pins>;
631 #address-cells = <1>;
632 #size-cells = <0>;
637 compatible = "qcom,i2c-qup-v2.1.1";
641 clock-names = "core", "iface";
642 pinctrl-names = "default";
643 pinctrl-0 = <&blsp1_i2c3_pins>;
644 #address-cells = <1>;
645 #size-cells = <0>;
650 compatible = "qcom,i2c-qup-v2.1.1";
654 clock-names = "core", "iface";
655 pinctrl-names = "default";
656 pinctrl-0 = <&blsp1_i2c4_pins>;
657 #address-cells = <1>;
658 #size-cells = <0>;
663 compatible = "qcom,i2c-qup-v2.1.1";
667 clock-names = "core", "iface";
668 pinctrl-names = "default";
669 pinctrl-0 = <&blsp1_i2c5_pins>;
670 #address-cells = <1>;
671 #size-cells = <0>;
676 compatible = "qcom,i2c-qup-v2.1.1";
681 clock-names = "core",
683 pinctrl-0 = <&blsp1_i2c6_pins>;
684 pinctrl-names = "default";
685 #address-cells = <1>;
686 #size-cells = <0>;
691 compatible = "qcom,ci-hdrc";
697 clock-names = "iface", "core";
698 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
699 assigned-clock-rates = <75000000>;
701 reset-names = "core";
704 hnp-disable;
705 srp-disable;
706 adp-disable;
707 ahb-burst-config = <0>;
708 phy-names = "usb-phy";
711 #reset-cells = <1>;
715 compatible = "qcom,usb-hs-phy-msm8226",
716 "qcom,usb-hs-phy";
717 #phy-cells = <0>;
720 clock-names = "ref", "sleep";
722 reset-names = "phy", "por";
723 qcom,init-seq = /bits/ 8 <0x0 0x44
733 clock-names = "core";
737 compatible = "qcom,msm8226-rpm-stats";
741 gcc: clock-controller@fc400000 {
742 compatible = "qcom,gcc-msm8226";
744 #clock-cells = <1>;
745 #reset-cells = <1>;
746 #power-domain-cells = <1>;
750 clock-names = "xo",
755 compatible = "qcom,rpm-msg-ram";
758 #address-cells = <1>;
759 #size-cells = <1>;
779 tsens: thermal-sensor@fc4a9000 {
780 compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1";
783 nvmem-cells = <&tsens_mode>,
792 nvmem-cell-names = "mode",
803 interrupt-names = "uplow";
804 #thermal-sensor-cells = <1>;
813 compatible = "qcom,msm8226-qfprom", "qcom,qfprom";
815 #address-cells = <1>;
816 #size-cells = <1>;
823 tsens_s0_p1: s0-p1@1c2 {
828 tsens_s1_p1: s1-p1@1c4 {
833 tsens_s2_p1: s2-p1@1c4 {
838 tsens_s3_p1: s3-p1@1c5 {
843 tsens_s4_p1: s4-p1@1c6 {
848 tsens_s5_p1: s5-p1@1c7 {
853 tsens_s6_p1: s6-p1@1ca {
863 tsens_s0_p2: s0-p2@1cd {
868 tsens_s1_p2: s1-p2@1cd {
873 tsens_s2_p2: s2-p2@1ce {
878 tsens_s3_p2: s3-p2@1cf {
883 tsens_s4_p2: s4-p2@446 {
888 tsens_s5_p2: s5-p2@447 {
893 tsens_s6_p2: s6-p2@44e {
905 compatible = "qcom,spmi-pmic-arb";
906 reg-names = "core", "intr", "cnfg";
910 interrupt-names = "periph_irq";
914 #address-cells = <2>;
915 #size-cells = <0>;
916 interrupt-controller;
917 #interrupt-cells = <4>;
920 bam_dmux_dma: dma-controller@fc834000 {
921 compatible = "qcom,bam-v1.4.0";
924 #dma-cells = <1>;
927 num-channels = <6>;
928 qcom,num-ees = <1>;
929 qcom,powered-remotely;
933 compatible = "qcom,msm8226-mss-pil";
936 reg-names = "qdsp6",
939 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
944 interrupt-names = "wdog",
948 "stop-ack";
954 clock-names = "iface",
960 reset-names = "mss_restart";
962 power-domains = <&rpmpd MSM8226_VDDCX>;
963 power-domain-names = "cx";
965 qcom,ext-bhs-reg = <&tcsr_regs_1 0x194>;
966 qcom,halt-regs = <&tcsr_regs_1 0x180 0x200 0x280>;
968 qcom,smem-states = <&modem_smp2p_out 0>;
969 qcom,smem-state-names = "stop";
971 memory-region = <&mba_region>, <&mpss_region>;
975 bam_dmux: bam-dmux {
976 compatible = "qcom,bam-dmux";
978 interrupt-parent = <&modem_smsm>;
980 interrupt-names = "pc", "pc-ack";
982 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
983 qcom,smem-state-names = "pc", "pc-ack";
986 dma-names = "tx", "rx";
989 smd-edge {
993 qcom,smd-edge = <0>;
1000 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
1002 #hwlock-cells = <1>;
1006 compatible = "qcom,tcsr-msm8226", "syscon";
1011 compatible = "qcom,msm8226-pinctrl";
1013 gpio-controller;
1014 #gpio-cells = <2>;
1015 gpio-ranges = <&tlmm 0 0 117>;
1016 interrupt-controller;
1017 #interrupt-cells = <2>;
1020 blsp1_i2c1_pins: blsp1-i2c1-state {
1023 drive-strength = <2>;
1024 bias-disable;
1027 blsp1_i2c2_pins: blsp1-i2c2-state {
1030 drive-strength = <2>;
1031 bias-disable;
1034 blsp1_i2c3_pins: blsp1-i2c3-state {
1037 drive-strength = <2>;
1038 bias-disable;
1041 blsp1_i2c4_pins: blsp1-i2c4-state {
1044 drive-strength = <2>;
1045 bias-disable;
1048 blsp1_i2c5_pins: blsp1-i2c5-state {
1051 drive-strength = <2>;
1052 bias-disable;
1055 blsp1_i2c6_pins: blsp1-i2c6-state {
1058 drive-strength = <2>;
1059 bias-disable;
1062 cci_default: cci-default-state {
1066 drive-strength = <2>;
1067 bias-disable;
1070 cci_sleep: cci-sleep-state {
1074 drive-strength = <2>;
1075 bias-disable;
1078 sdhc1_default_state: sdhc1-default-state {
1079 clk-pins {
1081 drive-strength = <10>;
1082 bias-disable;
1085 cmd-data-pins {
1087 drive-strength = <10>;
1088 bias-pull-up;
1092 sdhc2_default_state: sdhc2-default-state {
1093 clk-pins {
1095 drive-strength = <10>;
1096 bias-disable;
1099 cmd-data-pins {
1101 drive-strength = <10>;
1102 bias-pull-up;
1106 sdhc3_default_state: sdhc3-default-state {
1107 clk-pins {
1110 drive-strength = <8>;
1111 bias-disable;
1114 cmd-pins {
1117 drive-strength = <8>;
1118 bias-pull-up;
1121 data-pins {
1124 drive-strength = <8>;
1125 bias-pull-up;
1130 mmcc: clock-controller@fd8c0000 {
1131 compatible = "qcom,mmcc-msm8226";
1133 #clock-cells = <1>;
1134 #reset-cells = <1>;
1135 #power-domain-cells = <1>;
1144 clock-names = "xo",
1153 mdss: display-subsystem@fd900000 {
1156 reg-names = "mdss_phys", "vbif_phys";
1158 power-domains = <&mmcc MDSS_GDSC>;
1163 clock-names = "iface",
1169 interrupt-controller;
1170 #interrupt-cells = <1>;
1172 #address-cells = <1>;
1173 #size-cells = <1>;
1178 mdss_mdp: display-controller@fd900000 {
1179 compatible = "qcom,msm8226-mdp5", "qcom,mdp5";
1181 reg-names = "mdp_phys";
1183 interrupt-parent = <&mdss>;
1190 clock-names = "iface",
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1202 remote-endpoint = <&mdss_dsi0_in>;
1209 compatible = "qcom,msm8226-dsi-ctrl",
1210 "qcom,mdss-dsi-ctrl";
1212 reg-names = "dsi_ctrl";
1214 interrupt-parent = <&mdss>;
1217 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1219 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1229 clock-names = "mdp_core",
1239 #address-cells = <1>;
1240 #size-cells = <0>;
1243 #address-cells = <1>;
1244 #size-cells = <0>;
1249 remote-endpoint = <&mdss_mdp_intf1_out>;
1262 compatible = "qcom,dsi-phy-28nm-8226";
1266 reg-names = "dsi_pll",
1270 #clock-cells = <1>;
1271 #phy-cells = <0>;
1275 clock-names = "iface",
1281 compatible = "qcom,msm8226-cci";
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1289 clock-names = "camss_top_ahb",
1293 pinctrl-names = "default", "sleep";
1294 pinctrl-0 = <&cci_default>;
1295 pinctrl-1 = <&cci_sleep>;
1299 cci_i2c0: i2c-bus@0 {
1301 clock-frequency = <400000>;
1302 #address-cells = <1>;
1303 #size-cells = <0>;
1308 compatible = "qcom,adreno-305.18", "qcom,adreno";
1310 reg-names = "kgsl_3d0_reg_memory";
1313 interrupt-names = "kgsl_3d0_irq";
1318 clock-names = "core", "iface", "mem_iface";
1321 power-domains = <&mmcc OXILICX_GDSC>;
1322 operating-points-v2 = <&gpu_opp_table>;
1326 gpu_opp_table: opp-table {
1327 compatible = "operating-points-v2";
1329 opp-450000000 {
1330 opp-hz = /bits/ 64 <450000000>;
1333 opp-320000000 {
1334 opp-hz = /bits/ 64 <320000000>;
1337 opp-200000000 {
1338 opp-hz = /bits/ 64 <200000000>;
1341 opp-19000000 {
1342 opp-hz = /bits/ 64 <19000000>;
1348 compatible = "qcom,msm8226-ocmem";
1351 reg-names = "ctrl", "mem";
1354 clock-names = "core";
1356 #address-cells = <1>;
1357 #size-cells = <1>;
1359 gmu_sram: gmu-sram@0 {
1365 compatible = "qcom,msm8226-adsp-pil";
1368 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
1373 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1375 power-domains = <&rpmpd MSM8226_VDDCX>;
1376 power-domain-names = "cx";
1379 clock-names = "xo";
1381 memory-region = <&adsp_region>;
1383 qcom,smem-states = <&adsp_smp2p_out 0>;
1384 qcom,smem-state-names = "stop";
1388 smd-edge {
1392 qcom,smd-edge = <1>;
1399 compatible = "qcom,msm8226-imem", "syscon", "simple-mfd";
1402 reboot-mode {
1403 compatible = "syscon-reboot-mode";
1406 mode-bootloader = <0x77665500>;
1407 mode-normal = <0x77665501>;
1408 mode-recovery = <0x77665502>;
1413 thermal-zones {
1414 cpu0-thermal {
1415 polling-delay-passive = <250>;
1416 polling-delay = <1000>;
1418 thermal-sensors = <&tsens 5>;
1420 cooling-maps {
1423 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1445 cpu1-thermal {
1446 polling-delay-passive = <250>;
1447 polling-delay = <1000>;
1449 thermal-sensors = <&tsens 2>;
1451 cooling-maps {
1454 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1478 compatible = "arm,armv7-timer";