Lines Matching +full:adsp +full:- +full:pil +full:- +full:mode
1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
15 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&intc>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <19200000>;
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <32768>;
39 #address-cells = <1>;
40 #size-cells = <0>;
43 compatible = "arm,cortex-a7";
44 enable-method = "qcom,msm8226-smp";
47 next-level-cache = <&L2>;
49 operating-points-v2 = <&cpu_opp_table>;
52 #cooling-cells = <2>;
56 compatible = "arm,cortex-a7";
57 enable-method = "qcom,msm8226-smp";
60 next-level-cache = <&L2>;
62 operating-points-v2 = <&cpu_opp_table>;
65 #cooling-cells = <2>;
69 compatible = "arm,cortex-a7";
70 enable-method = "qcom,msm8226-smp";
73 next-level-cache = <&L2>;
75 operating-points-v2 = <&cpu_opp_table>;
78 #cooling-cells = <2>;
82 compatible = "arm,cortex-a7";
83 enable-method = "qcom,msm8226-smp";
86 next-level-cache = <&L2>;
88 operating-points-v2 = <&cpu_opp_table>;
91 #cooling-cells = <2>;
94 L2: l2-cache {
96 cache-level = <2>;
97 cache-unified;
103 compatible = "qcom,scm-msm8226", "qcom,scm";
105 clock-names = "core", "bus", "iface";
114 cpu_opp_table: opp-table-cpu {
115 compatible = "operating-points-v2";
116 opp-shared;
118 opp-300000000 {
119 opp-hz = /bits/ 64 <300000000>;
122 opp-384000000 {
123 opp-hz = /bits/ 64 <384000000>;
126 opp-600000000 {
127 opp-hz = /bits/ 64 <600000000>;
130 opp-787200000 {
131 opp-hz = /bits/ 64 <787200000>;
138 compatible = "arm,cortex-a7-pmu";
144 compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc";
146 master-stats {
147 compatible = "qcom,rpm-master-stats";
148 qcom,rpm-msg-ram = <&apss_master_stats>,
152 qcom,master-names = "APSS",
158 smd-edge {
161 qcom,smd-edge = <15>;
163 rpm_requests: rpm-requests {
164 compatible = "qcom,rpm-msm8226", "qcom,smd-rpm";
165 qcom,smd-channels = "rpm_requests";
167 rpmcc: clock-controller {
168 compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc";
169 #clock-cells = <1>;
171 clock-names = "xo";
174 rpmpd: power-controller {
175 compatible = "qcom,msm8226-rpmpd";
176 #power-domain-cells = <1>;
177 operating-points-v2 = <&rpmpd_opp_table>;
179 rpmpd_opp_table: opp-table {
180 compatible = "operating-points-v2";
183 opp-level = <1>;
186 opp-level = <2>;
189 opp-level = <3>;
192 opp-level = <4>;
195 opp-level = <5>;
198 opp-level = <6>;
206 reserved-memory {
207 #address-cells = <1>;
208 #size-cells = <1>;
213 no-map;
216 adsp_region: adsp@dc00000 {
218 no-map;
225 memory-region = <&smem_region>;
226 qcom,rpm-msg-ram = <&rpm_msg_ram>;
231 smp2p-adsp {
235 interrupt-parent = <&intc>;
240 qcom,local-pid = <0>;
241 qcom,remote-pid = <2>;
243 adsp_smp2p_out: master-kernel {
244 qcom,entry-name = "master-kernel";
245 #qcom,smem-state-cells = <1>;
248 adsp_smp2p_in: slave-kernel {
249 qcom,entry-name = "slave-kernel";
251 interrupt-controller;
252 #interrupt-cells = <2>;
257 compatible = "simple-bus";
258 #address-cells = <1>;
259 #size-cells = <1>;
262 intc: interrupt-controller@f9000000 {
263 compatible = "qcom,msm-qgic2";
266 interrupt-controller;
267 #interrupt-cells = <3>;
271 compatible = "qcom,msm8226-apcs-kpss-global",
272 "qcom,msm8916-apcs-kpss-global", "syscon";
274 #mbox-cells = <1>;
276 clock-names = "pll", "aux";
277 #clock-cells = <0>;
281 compatible = "qcom,msm8226-a7pll";
283 #clock-cells = <0>;
285 clock-names = "xo";
286 operating-points-v2 = <&a7pll_opp_table>;
288 a7pll_opp_table: opp-table {
289 compatible = "operating-points-v2";
291 opp-768000000 {
292 opp-hz = /bits/ 64 <768000000>;
295 opp-787200000 {
296 opp-hz = /bits/ 64 <787200000>;
299 opp-998400000 {
300 opp-hz = /bits/ 64 <998400000>;
303 opp-1094400000 {
304 opp-hz = /bits/ 64 <1094400000>;
307 opp-1190400000 {
308 opp-hz = /bits/ 64 <1190400000>;
311 opp-1305600000 {
312 opp-hz = /bits/ 64 <1305600000>;
315 opp-1344000000 {
316 opp-hz = /bits/ 64 <1344000000>;
319 opp-1401600000 {
320 opp-hz = /bits/ 64 <1401600000>;
323 opp-1497600000 {
324 opp-hz = /bits/ 64 <1497600000>;
327 opp-1593600000 {
328 opp-hz = /bits/ 64 <1593600000>;
331 opp-1689600000 {
332 opp-hz = /bits/ 64 <1689600000>;
335 opp-1785600000 {
336 opp-hz = /bits/ 64 <1785600000>;
341 saw_l2: power-manager@f9012000 {
342 compatible = "qcom,msm8226-saw2-v2.1-l2", "qcom,saw2";
347 compatible = "qcom,apss-wdt-msm8226", "qcom,kpss-wdt";
355 compatible = "arm,armv7-timer-mem";
357 #address-cells = <1>;
358 #size-cells = <1>;
362 frame-number = <0>;
370 frame-number = <1>;
377 frame-number = <2>;
384 frame-number = <3>;
391 frame-number = <4>;
398 frame-number = <5>;
405 frame-number = <6>;
412 acc0: power-manager@f9088000 {
413 compatible = "qcom,kpss-acc-v2";
417 saw0: power-manager@f9089000 {
418 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
422 acc1: power-manager@f9098000 {
423 compatible = "qcom,kpss-acc-v2";
427 saw1: power-manager@f9099000 {
428 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
432 acc2: power-manager@f90a8000 {
433 compatible = "qcom,kpss-acc-v2";
437 saw2: power-manager@f90a9000 {
438 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
442 acc3: power-manager@f90b8000 {
443 compatible = "qcom,kpss-acc-v2";
447 saw3: power-manager@f90b9000 {
448 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
453 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
455 reg-names = "hc", "core";
458 interrupt-names = "hc_irq", "pwr_irq";
462 clock-names = "iface", "core", "xo";
463 pinctrl-names = "default";
464 pinctrl-0 = <&sdhc1_default_state>;
469 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
471 reg-names = "hc", "core";
474 interrupt-names = "hc_irq", "pwr_irq";
478 clock-names = "iface", "core", "xo";
479 pinctrl-names = "default";
480 pinctrl-0 = <&sdhc3_default_state>;
485 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
487 reg-names = "hc", "core";
490 interrupt-names = "hc_irq", "pwr_irq";
494 clock-names = "iface", "core", "xo";
495 pinctrl-names = "default";
496 pinctrl-0 = <&sdhc2_default_state>;
501 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
505 clock-names = "core", "iface";
510 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
515 clock-names = "core",
521 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
525 clock-names = "core", "iface";
530 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
534 clock-names = "core", "iface";
539 compatible = "qcom,i2c-qup-v2.1.1";
543 clock-names = "core", "iface";
544 pinctrl-names = "default";
545 pinctrl-0 = <&blsp1_i2c1_pins>;
546 #address-cells = <1>;
547 #size-cells = <0>;
552 compatible = "qcom,i2c-qup-v2.1.1";
556 clock-names = "core", "iface";
557 pinctrl-names = "default";
558 pinctrl-0 = <&blsp1_i2c2_pins>;
559 #address-cells = <1>;
560 #size-cells = <0>;
565 compatible = "qcom,i2c-qup-v2.1.1";
569 clock-names = "core", "iface";
570 pinctrl-names = "default";
571 pinctrl-0 = <&blsp1_i2c3_pins>;
572 #address-cells = <1>;
573 #size-cells = <0>;
578 compatible = "qcom,i2c-qup-v2.1.1";
582 clock-names = "core", "iface";
583 pinctrl-names = "default";
584 pinctrl-0 = <&blsp1_i2c4_pins>;
585 #address-cells = <1>;
586 #size-cells = <0>;
591 compatible = "qcom,i2c-qup-v2.1.1";
595 clock-names = "core", "iface";
596 pinctrl-names = "default";
597 pinctrl-0 = <&blsp1_i2c5_pins>;
598 #address-cells = <1>;
599 #size-cells = <0>;
604 compatible = "qcom,i2c-qup-v2.1.1";
609 clock-names = "core",
611 pinctrl-0 = <&blsp1_i2c6_pins>;
612 pinctrl-names = "default";
613 #address-cells = <1>;
614 #size-cells = <0>;
619 compatible = "qcom,ci-hdrc";
625 clock-names = "iface", "core";
626 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
627 assigned-clock-rates = <75000000>;
629 reset-names = "core";
632 hnp-disable;
633 srp-disable;
634 adp-disable;
635 ahb-burst-config = <0>;
636 phy-names = "usb-phy";
639 #reset-cells = <1>;
643 compatible = "qcom,usb-hs-phy-msm8226",
644 "qcom,usb-hs-phy";
645 #phy-cells = <0>;
648 clock-names = "ref", "sleep";
650 reset-names = "phy", "por";
651 qcom,init-seq = /bits/ 8 <0x0 0x44
661 clock-names = "core";
665 compatible = "qcom,msm8226-rpm-stats";
669 gcc: clock-controller@fc400000 {
670 compatible = "qcom,gcc-msm8226";
672 #clock-cells = <1>;
673 #reset-cells = <1>;
674 #power-domain-cells = <1>;
678 clock-names = "xo",
683 compatible = "qcom,rpm-msg-ram";
686 #address-cells = <1>;
687 #size-cells = <1>;
707 tsens: thermal-sensor@fc4a9000 {
708 compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1";
711 nvmem-cells = <&tsens_mode>,
720 nvmem-cell-names = "mode",
731 interrupt-names = "uplow";
732 #thermal-sensor-cells = <1>;
741 compatible = "qcom,msm8226-qfprom", "qcom,qfprom";
743 #address-cells = <1>;
744 #size-cells = <1>;
751 tsens_s0_p1: s0-p1@1c2 {
756 tsens_s1_p1: s1-p1@1c4 {
761 tsens_s2_p1: s2-p1@1c4 {
766 tsens_s3_p1: s3-p1@1c5 {
771 tsens_s4_p1: s4-p1@1c6 {
776 tsens_s5_p1: s5-p1@1c7 {
781 tsens_s6_p1: s6-p1@1ca {
791 tsens_s0_p2: s0-p2@1cd {
796 tsens_s1_p2: s1-p2@1cd {
801 tsens_s2_p2: s2-p2@1ce {
806 tsens_s3_p2: s3-p2@1cf {
811 tsens_s4_p2: s4-p2@446 {
816 tsens_s5_p2: s5-p2@447 {
821 tsens_s6_p2: s6-p2@44e {
826 tsens_mode: mode@44f {
833 compatible = "qcom,spmi-pmic-arb";
834 reg-names = "core", "intr", "cnfg";
838 interrupt-names = "periph_irq";
842 #address-cells = <2>;
843 #size-cells = <0>;
844 interrupt-controller;
845 #interrupt-cells = <4>;
849 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
851 #hwlock-cells = <1>;
855 compatible = "qcom,msm8226-pinctrl";
857 gpio-controller;
858 #gpio-cells = <2>;
859 gpio-ranges = <&tlmm 0 0 117>;
860 interrupt-controller;
861 #interrupt-cells = <2>;
864 blsp1_i2c1_pins: blsp1-i2c1-state {
867 drive-strength = <2>;
868 bias-disable;
871 blsp1_i2c2_pins: blsp1-i2c2-state {
874 drive-strength = <2>;
875 bias-disable;
878 blsp1_i2c3_pins: blsp1-i2c3-state {
881 drive-strength = <2>;
882 bias-disable;
885 blsp1_i2c4_pins: blsp1-i2c4-state {
888 drive-strength = <2>;
889 bias-disable;
892 blsp1_i2c5_pins: blsp1-i2c5-state {
895 drive-strength = <2>;
896 bias-disable;
899 blsp1_i2c6_pins: blsp1-i2c6-state {
902 drive-strength = <2>;
903 bias-disable;
906 cci_default: cci-default-state {
910 drive-strength = <2>;
911 bias-disable;
914 cci_sleep: cci-sleep-state {
918 drive-strength = <2>;
919 bias-disable;
922 sdhc1_default_state: sdhc1-default-state {
923 clk-pins {
925 drive-strength = <10>;
926 bias-disable;
929 cmd-data-pins {
931 drive-strength = <10>;
932 bias-pull-up;
936 sdhc2_default_state: sdhc2-default-state {
937 clk-pins {
939 drive-strength = <10>;
940 bias-disable;
943 cmd-data-pins {
945 drive-strength = <10>;
946 bias-pull-up;
950 sdhc3_default_state: sdhc3-default-state {
951 clk-pins {
954 drive-strength = <8>;
955 bias-disable;
958 cmd-pins {
961 drive-strength = <8>;
962 bias-pull-up;
965 data-pins {
968 drive-strength = <8>;
969 bias-pull-up;
974 mmcc: clock-controller@fd8c0000 {
975 compatible = "qcom,mmcc-msm8226";
977 #clock-cells = <1>;
978 #reset-cells = <1>;
979 #power-domain-cells = <1>;
988 clock-names = "xo",
997 mdss: display-subsystem@fd900000 {
1000 reg-names = "mdss_phys", "vbif_phys";
1002 power-domains = <&mmcc MDSS_GDSC>;
1007 clock-names = "iface",
1013 interrupt-controller;
1014 #interrupt-cells = <1>;
1016 #address-cells = <1>;
1017 #size-cells = <1>;
1022 mdss_mdp: display-controller@fd900000 {
1023 compatible = "qcom,msm8226-mdp5", "qcom,mdp5";
1025 reg-names = "mdp_phys";
1027 interrupt-parent = <&mdss>;
1034 clock-names = "iface",
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1046 remote-endpoint = <&mdss_dsi0_in>;
1053 compatible = "qcom,msm8226-dsi-ctrl",
1054 "qcom,mdss-dsi-ctrl";
1056 reg-names = "dsi_ctrl";
1058 interrupt-parent = <&mdss>;
1061 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1063 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1073 clock-names = "mdp_core",
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1093 remote-endpoint = <&mdss_mdp_intf1_out>;
1106 compatible = "qcom,dsi-phy-28nm-8226";
1110 reg-names = "dsi_pll",
1114 #clock-cells = <1>;
1115 #phy-cells = <0>;
1119 clock-names = "iface",
1125 compatible = "qcom,msm8226-cci";
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1133 clock-names = "camss_top_ahb",
1137 pinctrl-names = "default", "sleep";
1138 pinctrl-0 = <&cci_default>;
1139 pinctrl-1 = <&cci_sleep>;
1143 cci_i2c0: i2c-bus@0 {
1145 clock-frequency = <400000>;
1146 #address-cells = <1>;
1147 #size-cells = <0>;
1152 compatible = "qcom,adreno-305.18", "qcom,adreno";
1154 reg-names = "kgsl_3d0_reg_memory";
1157 interrupt-names = "kgsl_3d0_irq";
1162 clock-names = "core", "iface", "mem_iface";
1165 power-domains = <&mmcc OXILICX_GDSC>;
1166 operating-points-v2 = <&gpu_opp_table>;
1170 gpu_opp_table: opp-table {
1171 compatible = "operating-points-v2";
1173 opp-450000000 {
1174 opp-hz = /bits/ 64 <450000000>;
1177 opp-320000000 {
1178 opp-hz = /bits/ 64 <320000000>;
1181 opp-200000000 {
1182 opp-hz = /bits/ 64 <200000000>;
1185 opp-19000000 {
1186 opp-hz = /bits/ 64 <19000000>;
1192 compatible = "qcom,msm8226-ocmem";
1195 reg-names = "ctrl", "mem";
1198 clock-names = "core";
1200 #address-cells = <1>;
1201 #size-cells = <1>;
1203 gmu_sram: gmu-sram@0 {
1208 adsp: remoteproc@fe200000 { label
1209 compatible = "qcom,msm8226-adsp-pil";
1212 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
1217 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1219 power-domains = <&rpmpd MSM8226_VDDCX>;
1220 power-domain-names = "cx";
1223 clock-names = "xo";
1225 memory-region = <&adsp_region>;
1227 qcom,smem-states = <&adsp_smp2p_out 0>;
1228 qcom,smem-state-names = "stop";
1232 smd-edge {
1236 qcom,smd-edge = <1>;
1243 compatible = "qcom,msm8226-imem", "syscon", "simple-mfd";
1246 reboot-mode {
1247 compatible = "syscon-reboot-mode";
1250 mode-bootloader = <0x77665500>;
1251 mode-normal = <0x77665501>;
1252 mode-recovery = <0x77665502>;
1257 thermal-zones {
1258 cpu0-thermal {
1259 polling-delay-passive = <250>;
1260 polling-delay = <1000>;
1262 thermal-sensors = <&tsens 5>;
1264 cooling-maps {
1267 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1289 cpu1-thermal {
1290 polling-delay-passive = <250>;
1291 polling-delay = <1000>;
1293 thermal-sensors = <&tsens 2>;
1295 cooling-maps {
1298 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1322 compatible = "arm,armv7-timer";