Lines Matching +full:0 +full:xf9089000
27 #clock-cells = <0>;
33 #clock-cells = <0>;
40 #size-cells = <0>;
42 cpu0: cpu@0 {
46 reg = <0>;
109 memory@0 {
111 reg = <0x0 0x0>;
160 mboxes = <&apcs 0>;
212 reg = <0x3000000 0x100000>;
217 reg = <0x0dc00000 0x1900000>;
240 qcom,local-pid = <0>;
264 reg = <0xf9000000 0x1000>,
265 <0xf9002000 0x1000>;
273 reg = <0xf9011000 0x1000>;
277 #clock-cells = <0>;
282 reg = <0xf9016000 0x40>;
283 #clock-cells = <0>;
343 reg = <0xf9012000 0x1000>;
348 reg = <0xf9017000 0x1000>;
356 reg = <0xf9020000 0x1000>;
362 frame-number = <0>;
365 reg = <0xf9021000 0x1000>,
366 <0xf9022000 0x1000>;
372 reg = <0xf9023000 0x1000>;
379 reg = <0xf9024000 0x1000>;
386 reg = <0xf9025000 0x1000>;
393 reg = <0xf9026000 0x1000>;
400 reg = <0xf9027000 0x1000>;
407 reg = <0xf9028000 0x1000>;
414 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
419 reg = <0xf9089000 0x1000>;
424 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
429 reg = <0xf9099000 0x1000>;
434 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
439 reg = <0xf90a9000 0x1000>;
444 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
449 reg = <0xf90b9000 0x1000>;
454 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
464 pinctrl-0 = <&sdhc1_default_state>;
470 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
480 pinctrl-0 = <&sdhc3_default_state>;
486 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
496 pinctrl-0 = <&sdhc2_default_state>;
502 reg = <0xf991d000 0x1000>;
511 reg = <0xf991e000 0x1000>;
522 reg = <0xf991f000 0x1000>;
531 reg = <0xf9920000 0x1000>;
540 reg = <0xf9923000 0x1000>;
545 pinctrl-0 = <&blsp1_i2c1_pins>;
547 #size-cells = <0>;
553 reg = <0xf9924000 0x1000>;
558 pinctrl-0 = <&blsp1_i2c2_pins>;
560 #size-cells = <0>;
566 reg = <0xf9925000 0x1000>;
571 pinctrl-0 = <&blsp1_i2c3_pins>;
573 #size-cells = <0>;
579 reg = <0xf9926000 0x1000>;
584 pinctrl-0 = <&blsp1_i2c4_pins>;
586 #size-cells = <0>;
592 reg = <0xf9927000 0x1000>;
597 pinctrl-0 = <&blsp1_i2c5_pins>;
599 #size-cells = <0>;
605 reg = <0xf9928000 0x1000>;
611 pinctrl-0 = <&blsp1_i2c6_pins>;
614 #size-cells = <0>;
620 reg = <0xf9a55000 0x200>,
621 <0xf9a55200 0x200>;
635 ahb-burst-config = <0>;
645 #phy-cells = <0>;
649 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
651 qcom,init-seq = /bits/ 8 <0x0 0x44
652 0x1 0x68 0x2 0x24 0x3 0x13>;
659 reg = <0xf9bff000 0x200>;
666 reg = <0xfc190000 0x10000>;
671 reg = <0xfc400000 0x4000>;
684 reg = <0xfc428000 0x4000>;
688 ranges = <0 0xfc428000 0x4000>;
691 reg = <0x150 0x14>;
695 reg = <0xb50 0x14>;
699 reg = <0x1550 0x14>;
703 reg = <0x1f50 0x14>;
709 reg = <0xfc4a9000 0x1000>, /* TM */
710 <0xfc4a8000 0x1000>; /* SROT */
737 reg = <0xfc4ab000 0x4>;
742 reg = <0xfc4bc000 0x1000>;
747 reg = <0x1c1 0x2>;
752 reg = <0x1c2 0x2>;
757 reg = <0x1c4 0x1>;
758 bits = <0 6>;
762 reg = <0x1c4 0x2>;
767 reg = <0x1c5 0x2>;
772 reg = <0x1c6 0x1>;
777 reg = <0x1c7 0x1>;
778 bits = <0 6>;
782 reg = <0x1ca 0x2>;
787 reg = <0x1cc 0x1>;
788 bits = <0 8>;
792 reg = <0x1cd 0x1>;
793 bits = <0 6>;
797 reg = <0x1cd 0x2>;
802 reg = <0x1ce 0x2>;
807 reg = <0x1cf 0x1>;
812 reg = <0x446 0x2>;
817 reg = <0x447 0x1>;
822 reg = <0x44e 0x1>;
827 reg = <0x44f 0x1>;
835 reg = <0xfc4cf000 0x1000>,
836 <0xfc4cb000 0x1000>,
837 <0xfc4ca000 0x1000>;
840 qcom,ee = <0>;
841 qcom,channel = <0>;
843 #size-cells = <0>;
850 reg = <0xfd484000 0x1000>;
856 reg = <0xfd510000 0x4000>;
859 gpio-ranges = <&tlmm 0 0 117>;
976 reg = <0xfd8c0000 0x6000>;
987 <&mdss_dsi0_phy 0>;
999 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1024 reg = <0xfd900100 0x22000>;
1028 interrupts = <0>;
1041 #size-cells = <0>;
1043 port@0 {
1044 reg = <0>;
1055 reg = <0xfd922800 0x1f8>;
1063 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1084 #size-cells = <0>;
1088 #size-cells = <0>;
1090 port@0 {
1091 reg = <0>;
1107 reg = <0xfd922a00 0xd4>,
1108 <0xfd922b00 0x280>,
1109 <0xfd922d80 0x30>;
1115 #phy-cells = <0>;
1126 reg = <0xfda0c000 0x1000>;
1128 #size-cells = <0>;
1138 pinctrl-0 = <&cci_default>;
1143 cci_i2c0: i2c-bus@0 {
1144 reg = <0>;
1147 #size-cells = <0>;
1153 reg = <0xfdb00000 0x10000>;
1193 reg = <0xfdd00000 0x2000>,
1194 <0xfec00000 0x20000>;
1196 ranges = <0 0xfec00000 0x20000>;
1203 gmu_sram: gmu-sram@0 {
1204 reg = <0x0 0x20000>;
1210 reg = <0xfe200000 0x100>;
1213 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1227 qcom,smem-states = <&adsp_smp2p_out 0>;
1244 reg = <0xfe805000 0x1000>;
1248 offset = <0x65c>;
1250 mode-bootloader = <0x77665500>;
1251 mode-normal = <0x77665501>;
1252 mode-recovery = <0x77665502>;