Lines Matching +full:msm +full:- +full:uartdm
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
13 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
14 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
15 #include <dt-bindings/mfd/qcom-rpm.h>
16 #include <dt-bindings/soc/qcom,gsbi.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
23 interrupt-parent = <&intc>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a5";
33 next-level-cache = <&L2>;
37 cpu-pmu {
38 compatible = "arm,cortex-a5-pmu";
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <19200000>;
50 vsdcc_fixed: vsdcc-regulator {
51 compatible = "regulator-fixed";
52 regulator-name = "SDCC Power";
53 regulator-min-microvolt = <2700000>;
54 regulator-max-microvolt = <2700000>;
55 regulator-always-on;
59 #address-cells = <1>;
60 #size-cells = <1>;
62 compatible = "simple-bus";
64 L2: cache-controller@2040000 {
65 compatible = "arm,pl310-cache";
67 arm,data-latency = <2 2 0>;
68 cache-unified;
69 cache-level = <2>;
72 intc: interrupt-controller@2000000 {
73 compatible = "qcom,msm-qgic2";
74 interrupt-controller;
75 #interrupt-cells = <3>;
81 compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer",
82 "qcom,msm-timer";
87 clock-frequency = <27000000>;
88 cpu-offset = <0x80000>;
92 compatible = "qcom,mdm9615-pinctrl";
93 gpio-controller;
94 gpio-ranges = <&msmgpio 0 0 88>;
95 #gpio-cells = <2>;
97 interrupt-controller;
98 #interrupt-cells = <2>;
102 gcc: clock-controller@900000 {
103 compatible = "qcom,gcc-mdm9615";
104 #clock-cells = <1>;
105 #reset-cells = <1>;
111 lcc: clock-controller@28000000 {
112 compatible = "qcom,lcc-mdm9615";
114 #clock-cells = <1>;
115 #reset-cells = <1>;
122 clock-names = "cxo",
132 l2cc: clock-controller@2011000 {
133 compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
141 clock-names = "core";
142 assigned-clocks = <&gcc PRNG_CLK>;
143 assigned-clock-rates = <32000000>;
147 compatible = "qcom,gsbi-v1.0.0";
148 cell-index = <2>;
151 clock-names = "iface";
153 #address-cells = <1>;
154 #size-cells = <1>;
158 compatible = "qcom,i2c-qup-v1.1.1";
159 #address-cells = <1>;
160 #size-cells = <0>;
165 clock-names = "core", "iface";
171 compatible = "qcom,gsbi-v1.0.0";
172 cell-index = <3>;
175 clock-names = "iface";
177 #address-cells = <1>;
178 #size-cells = <1>;
182 compatible = "qcom,spi-qup-v1.1.1";
183 #address-cells = <1>;
184 #size-cells = <0>;
189 clock-names = "core", "iface";
195 compatible = "qcom,gsbi-v1.0.0";
196 cell-index = <4>;
199 clock-names = "iface";
201 #address-cells = <1>;
202 #size-cells = <1>;
205 syscon-tcsr = <&tcsr>;
208 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
213 clock-names = "core", "iface";
219 compatible = "qcom,gsbi-v1.0.0";
220 cell-index = <5>;
223 clock-names = "iface";
225 #address-cells = <1>;
226 #size-cells = <1>;
229 syscon-tcsr = <&tcsr>;
232 compatible = "qcom,i2c-qup-v1.1.1";
233 #address-cells = <1>;
234 #size-cells = <0>;
239 assigned-clocks = <&gcc GSBI5_QUP_CLK>;
240 assigned-clock-rates = <24000000>;
243 clock-names = "core", "iface";
248 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
253 clock-names = "core", "iface";
261 qcom,controller-type = "pmic-arbiter";
264 sdcc1bam: dma-controller@12182000 {
265 compatible = "qcom,bam-v1.3.0";
269 clock-names = "bam_clk";
270 #dma-cells = <1>;
274 sdcc2bam: dma-controller@12142000 {
275 compatible = "qcom,bam-v1.3.0";
279 clock-names = "bam_clk";
280 #dma-cells = <1>;
287 arm,primecell-periphid = <0x00051180>;
291 clock-names = "mclk", "apb_pclk";
292 bus-width = <8>;
293 max-frequency = <48000000>;
294 cap-sd-highspeed;
295 cap-mmc-highspeed;
296 vmmc-supply = <&vsdcc_fixed>;
298 dma-names = "tx", "rx";
299 assigned-clocks = <&gcc SDC1_CLK>;
300 assigned-clock-rates = <400000>;
305 arm,primecell-periphid = <0x00051180>;
310 clock-names = "mclk", "apb_pclk";
311 bus-width = <4>;
312 cap-sd-highspeed;
313 cap-mmc-highspeed;
314 max-frequency = <48000000>;
315 no-1-8-v;
316 vmmc-supply = <&vsdcc_fixed>;
318 dma-names = "tx", "rx";
319 assigned-clocks = <&gcc SDC2_CLK>;
320 assigned-clock-rates = <400000>;
324 compatible = "qcom,tcsr-mdm9615", "syscon";
329 compatible = "qcom,rpm-mdm9615";
337 interrupt-names = "ack", "err", "wakeup";