Lines Matching +full:0 +full:x1b800000
23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
54 polling-delay-passive = <0>;
55 polling-delay = <0>;
56 thermal-sensors = <&tsens 0>;
74 polling-delay-passive = <0>;
75 polling-delay = <0>;
94 polling-delay-passive = <0>;
95 polling-delay = <0>;
114 polling-delay-passive = <0>;
115 polling-delay = <0>;
134 polling-delay-passive = <0>;
135 polling-delay = <0>;
154 polling-delay-passive = <0>;
155 polling-delay = <0>;
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
194 polling-delay-passive = <0>;
195 polling-delay = <0>;
214 polling-delay-passive = <0>;
215 polling-delay = <0>;
234 polling-delay-passive = <0>;
235 polling-delay = <0>;
254 polling-delay-passive = <0>;
255 polling-delay = <0>;
276 reg = <0x0 0x0>;
291 reg = <0x40000000 0x1000000>;
297 reg = <0x41000000 0x200000>;
307 #clock-cells = <0>;
313 #clock-cells = <0>;
320 #clock-cells = <0>;
333 snps,blen = <16 0 0 0 0 0 0>;
352 reg = <0x00108000 0x1000>;
353 qcom,ipc = <&l2cc 0x8 2>;
371 reg = <0x00500000 0x1000>;
377 reg = <0x00700000 0x1000>;
381 reg = <0xc0 0x4>;
384 reg = <0x400 0xb>;
387 reg = <0x410 0xb>;
393 reg = <0x00800000 0x4000>;
396 gpio-ranges = <&qcom_pinmux 0 0 69>;
503 reg = <0x00900000 0x4000>;
522 reg = <0x01200600 0x100>;
531 reg = <0x02000000 0x1000>,
532 <0x02002000 0x1000>;
548 reg = <0x0200a000 0x100>;
552 cpu-offset = <0x80000>;
557 reg = <0x02011000 0x1000>;
560 #clock-cells = <0>;
565 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
569 #clock-cells = <0>;
574 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
579 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
583 #clock-cells = <0>;
588 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
593 reg = <0x03000000 0x0000FFFF>;
600 reg = <0x100f8800 0x8000>;
612 reg = <0x10000000 0xcd00>;
623 reg = <0x100f8800 0x30>;
626 #phy-cells = <0>;
633 reg = <0x100f8830 0x30>;
636 #phy-cells = <0>;
645 reg = <0x110f8800 0x8000>;
657 reg = <0x11000000 0xcd00>;
668 reg = <0x110f8800 0x30>;
671 #phy-cells = <0>;
678 reg = <0x110f8830 0x30>;
681 #phy-cells = <0>;
688 reg = <0x12182000 0x8000>;
693 qcom,ee = <0>;
698 reg = <0x12402000 0x8000>;
703 qcom,ee = <0>;
714 arm,primecell-periphid = <0x00051180>;
716 reg = <0x12180000 0x2000>;
734 arm,primecell-periphid = <0x00051180>;
735 reg = <0x12400000 0x2000>;
752 reg = <0x12440000 0x100>;
766 reg = <0x12450000 0x100>,
767 <0x12400000 0x03>;
777 reg = <0x12460000 0x1000>;
782 #size-cells = <0>;
791 reg = <0x12480000 0x100>;
803 reg = <0x12490000 0x1000>,
804 <0x12480000 0x1000>;
813 reg = <0x124a0000 0x1000>;
821 #size-cells = <0>;
828 reg = <0x16300000 0x100>;
840 reg = <0x16340000 0x1000>,
841 <0x16300000 0x1000>;
850 reg = <0x16380000 0x1000>;
858 #size-cells = <0>;
864 reg = <0x16500000 0x100>;
878 reg = <0x16580000 0x1000>;
885 #size-cells = <0>;
892 reg = <0x16580000 0x1000>;
899 #size-cells = <0>;
909 reg = <0x16600000 0x100>;
919 reg = <0x16640000 0x1000>,
920 <0x16600000 0x1000>;
929 reg = <0x16680000 0x1000>;
936 #size-cells = <0>;
944 reg = <0x18300000 0x100000>;
957 qcom,ee = <0>;
965 reg = <0x1a200000 0x100>;
978 reg = <0x1a240000 0x1000>,
979 <0x1a200000 0x1000>;
988 reg = <0x1a280000 0x1000>;
996 #size-cells = <0>;
1001 reg = <0x1a280000 0x1000>;
1009 #size-cells = <0>;
1015 reg = <0x1a400000 0x100>;
1020 reg = <0x1a500000 0x200>;
1027 reg = <0x1ac00000 0x800>;
1029 pinctrl-0 = <&nand_pins>;
1042 #size-cells = <0>;
1049 reg = <0x1b400000 0x200>;
1054 #phy-cells = <0>;
1060 reg = <0x1b500000 0x1000
1061 0x1b502000 0x80
1062 0x1b600000 0x100
1063 0x0ff00000 0x100000>;
1066 linux,pci-domain = <0>;
1067 bus-range = <0x00 0xff>;
1072 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */
1073 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */
1078 interrupt-map-mask = <0 0 0 0x7>;
1079 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1080 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1081 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1082 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1102 pinctrl-0 = <&pcie0_pins>;
1108 pcie@0 {
1110 reg = <0x0 0x0 0x0 0x0 0x0>;
1111 bus-range = <0x01 0xff>;
1121 reg = <0x1b700000 0x1000
1122 0x1b702000 0x80
1123 0x1b800000 0x100
1124 0x31f00000 0x100000>;
1128 bus-range = <0x00 0xff>;
1133 ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */
1134 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */
1139 interrupt-map-mask = <0 0 0 0x7>;
1140 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1141 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1142 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1143 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1163 pinctrl-0 = <&pcie1_pins>;
1169 pcie@0 {
1171 reg = <0x0 0x0 0x0 0x0 0x0>;
1172 bus-range = <0x01 0xff>;
1182 reg = <0x1b900000 0x1000
1183 0x1b902000 0x80
1184 0x1ba00000 0x100
1185 0x35f00000 0x100000>;
1189 bus-range = <0x00 0xff>;
1194 ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */
1195 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */
1200 interrupt-map-mask = <0 0 0 0x7>;
1201 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1202 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1203 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1204 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1224 pinctrl-0 = <&pcie2_pins>;
1230 pcie@0 {
1232 reg = <0x0 0x0 0x0 0x0 0x0>;
1233 bus-range = <0x01 0xff>;
1243 reg = <0x1bb00000 0x000001FF>;
1248 reg = <0x28000000 0x1000>;
1264 reg = <0x28100000 0x10000>;
1270 reg = <0x29000000 0x180>;
1293 reg = <0x37000000 0x200000>;
1317 reg = <0x37200000 0x200000>;
1341 reg = <0x37400000 0x200000>;
1365 reg = <0x37600000 0x200000>;