Lines Matching +full:bam +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 interrupt-parent = <&intc>;
20 reserved-memory {
21 #address-cells = <0x1>;
22 #size-cells = <0x1>;
27 no-map;
32 no-map;
44 #address-cells = <1>;
45 #size-cells = <0>;
48 compatible = "arm,cortex-a7";
49 enable-method = "qcom,kpss-acc-v2";
50 next-level-cache = <&L2>;
55 clock-frequency = <0>;
56 clock-latency = <256000>;
57 operating-points-v2 = <&cpu0_opp_table>;
62 compatible = "arm,cortex-a7";
63 enable-method = "qcom,kpss-acc-v2";
64 next-level-cache = <&L2>;
69 clock-frequency = <0>;
70 clock-latency = <256000>;
71 operating-points-v2 = <&cpu0_opp_table>;
76 compatible = "arm,cortex-a7";
77 enable-method = "qcom,kpss-acc-v2";
78 next-level-cache = <&L2>;
83 clock-frequency = <0>;
84 clock-latency = <256000>;
85 operating-points-v2 = <&cpu0_opp_table>;
90 compatible = "arm,cortex-a7";
91 enable-method = "qcom,kpss-acc-v2";
92 next-level-cache = <&L2>;
97 clock-frequency = <0>;
98 clock-latency = <256000>;
99 operating-points-v2 = <&cpu0_opp_table>;
102 L2: l2-cache {
104 cache-level = <2>;
105 cache-unified;
110 cpu0_opp_table: opp-table {
111 compatible = "operating-points-v2";
112 opp-shared;
114 opp-48000000 {
115 opp-hz = /bits/ 64 <48000000>;
116 clock-latency-ns = <256000>;
118 opp-200000000 {
119 opp-hz = /bits/ 64 <200000000>;
120 clock-latency-ns = <256000>;
122 opp-500000000 {
123 opp-hz = /bits/ 64 <500000000>;
124 clock-latency-ns = <256000>;
126 opp-716000000 {
127 opp-hz = /bits/ 64 <716000000>;
128 clock-latency-ns = <256000>;
138 compatible = "arm,cortex-a7-pmu";
145 compatible = "fixed-clock";
146 clock-frequency = <32000>;
147 #clock-cells = <0>;
151 compatible = "fixed-clock";
152 clock-frequency = <48000000>;
153 #clock-cells = <0>;
159 compatible = "qcom,scm-ipq4019", "qcom,scm";
164 compatible = "arm,armv7-timer";
169 clock-frequency = <48000000>;
170 always-on;
174 #address-cells = <1>;
175 #size-cells = <1>;
177 compatible = "simple-bus";
179 intc: interrupt-controller@b000000 {
180 compatible = "qcom,msm-qgic2";
181 interrupt-controller;
182 #interrupt-cells = <3>;
187 gcc: clock-controller@1800000 {
188 compatible = "qcom,gcc-ipq4019";
189 #clock-cells = <1>;
190 #reset-cells = <1>;
193 clock-names = "xo", "sleep_clk";
200 clock-names = "core";
205 compatible = "qcom,ipq4019-pinctrl";
207 gpio-controller;
208 gpio-ranges = <&tlmm 0 0 100>;
209 #gpio-cells = <2>;
210 interrupt-controller;
211 #interrupt-cells = <2>;
216 compatible = "qcom,vqmmc-ipq4019-regulator";
218 regulator-name = "vqmmc";
219 regulator-min-microvolt = <1500000>;
220 regulator-max-microvolt = <3000000>;
221 regulator-always-on;
226 compatible = "qcom,ipq4019-sdhci", "qcom,sdhci-msm-v4";
228 reg-names = "hc", "core";
230 interrupt-names = "hc_irq", "pwr_irq";
231 bus-width = <8>;
235 clock-names = "iface",
241 blsp_dma: dma-controller@7884000 {
242 compatible = "qcom,bam-v1.7.0";
246 clock-names = "bam_clk";
247 #dma-cells = <1>;
253 compatible = "qcom,spi-qup-v2.2.1";
258 clock-names = "core", "iface";
259 #address-cells = <1>;
260 #size-cells = <0>;
262 dma-names = "tx", "rx";
267 compatible = "qcom,spi-qup-v2.2.1";
272 clock-names = "core", "iface";
273 #address-cells = <1>;
274 #size-cells = <0>;
276 dma-names = "tx", "rx";
281 compatible = "qcom,i2c-qup-v2.2.1";
286 clock-names = "core", "iface";
287 #address-cells = <1>;
288 #size-cells = <0>;
290 dma-names = "tx", "rx";
295 compatible = "qcom,i2c-qup-v2.2.1";
300 clock-names = "core", "iface";
301 #address-cells = <1>;
302 #size-cells = <0>;
304 dma-names = "tx", "rx";
308 cryptobam: dma-controller@8e04000 {
309 compatible = "qcom,bam-v1.7.0";
313 clock-names = "bam_clk";
314 #dma-cells = <1>;
316 qcom,controlled-remotely;
321 compatible = "qcom,crypto-v5.1";
326 clock-names = "iface", "bus", "core";
328 dma-names = "rx", "tx";
332 acc0: power-manager@b088000 {
333 compatible = "qcom,kpss-acc-v2";
337 acc1: power-manager@b098000 {
338 compatible = "qcom,kpss-acc-v2";
342 acc2: power-manager@b0a8000 {
343 compatible = "qcom,kpss-acc-v2";
347 acc3: power-manager@b0b8000 {
348 compatible = "qcom,kpss-acc-v2";
352 saw0: power-manager@b089000 {
353 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
357 saw1: power-manager@b099000 {
358 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
362 saw2: power-manager@b0a9000 {
363 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
367 saw3: power-manager@b0b9000 {
368 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
372 saw_l2: power-manager@b012000 {
373 compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2";
378 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
384 clock-names = "core", "iface";
386 dma-names = "tx", "rx";
390 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
396 clock-names = "core", "iface";
398 dma-names = "tx", "rx";
402 compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt";
405 timeout-sec = <10>;
415 compatible = "qcom,pcie-ipq4019";
420 reg-names = "dbi", "elbi", "parf", "config";
422 linux,pci-domain = <0>;
423 bus-range = <0x00 0xff>;
424 num-lanes = <1>;
425 #address-cells = <3>;
426 #size-cells = <2>;
432 interrupt-names = "msi";
433 #interrupt-cells = <1>;
434 interrupt-map-mask = <0 0 0 0x7>;
435 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
442 clock-names = "aux",
458 reset-names = "axi_m",
476 bus-range = <0x01 0xff>;
478 #address-cells = <3>;
479 #size-cells = <2>;
484 qpic_bam: dma-controller@7984000 {
485 compatible = "qcom,bam-v1.7.0";
489 clock-names = "bam_clk";
490 #dma-cells = <1>;
495 nand: nand-controller@79b0000 {
496 compatible = "qcom,ipq4019-nand";
498 #address-cells = <1>;
499 #size-cells = <0>;
502 clock-names = "core", "aon";
507 dma-names = "tx", "rx", "cmd";
513 nand-ecc-strength = <4>;
514 nand-ecc-step-size = <512>;
515 nand-bus-width = <8>;
520 compatible = "qcom,ipq4019-wifi";
528 reset-names = "wifi_cpu_init", "wifi_radio_srif",
534 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
553 interrupt-names = "msi0", "msi1", "msi2", "msi3",
562 compatible = "qcom,ipq4019-wifi";
570 reset-names = "wifi_cpu_init", "wifi_radio_srif",
576 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
595 interrupt-names = "msi0", "msi1", "msi2", "msi3",
604 #address-cells = <1>;
605 #size-cells = <0>;
606 compatible = "qcom,ipq4019-mdio";
610 ethernet-phy-package@0 {
611 #address-cells = <1>;
612 #size-cells = <0>;
613 compatible = "qcom,qca8075-package";
616 qcom,tx-drive-strength-milliwatt = <300>;
618 ethphy0: ethernet-phy@0 {
622 ethphy1: ethernet-phy@1 {
626 ethphy2: ethernet-phy@2 {
630 ethphy3: ethernet-phy@3 {
634 ethphy4: ethernet-phy@4 {
640 usb3_ss_phy: usb-phy@9a000 {
641 compatible = "qcom,usb-ss-ipq4019-phy";
642 #phy-cells = <0>;
644 reg-names = "phy_base";
646 reset-names = "por_rst";
650 usb3_hs_phy: usb-phy@a6000 {
651 compatible = "qcom,usb-hs-ipq4019-phy";
652 #phy-cells = <0>;
654 reg-names = "phy_base";
656 reset-names = "por_rst", "srif_rst";
661 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
663 #address-cells = <1>;
664 #size-cells = <1>;
668 clock-names = "core", "sleep", "mock_utmi";
677 phy-names = "usb2-phy", "usb3-phy";
682 usb2_hs_phy: usb-phy@a8000 {
683 compatible = "qcom,usb-hs-ipq4019-phy";
684 #phy-cells = <0>;
686 reg-names = "phy_base";
688 reset-names = "por_rst", "srif_rst";
693 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
695 #address-cells = <1>;
696 #size-cells = <1>;
700 clock-names = "core", "sleep", "mock_utmi";
709 phy-names = "usb2-phy";