Lines Matching +full:0 +full:- +full:6
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&intc>;
15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
20 smem_mem: smem-region@fa00000 {
21 reg = <0xfa00000 0x200000>;
22 no-map;
27 #address-cells = <1>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 enable-method = "qcom,kpss-acc-v2";
35 next-level-cache = <&l2>;
38 cpu-idle-states = <&cpu_spc>;
45 enable-method = "qcom,kpss-acc-v2";
46 next-level-cache = <&l2>;
49 cpu-idle-states = <&cpu_spc>;
56 enable-method = "qcom,kpss-acc-v2";
57 next-level-cache = <&l2>;
60 cpu-idle-states = <&cpu_spc>;
67 enable-method = "qcom,kpss-acc-v2";
68 next-level-cache = <&l2>;
71 cpu-idle-states = <&cpu_spc>;
74 l2: l2-cache {
76 cache-level = <2>;
77 cache-unified;
81 idle-states {
82 cpu_spc: cpu-spc {
83 compatible = "qcom,idle-state-spc",
84 "arm,idle-state";
85 entry-latency-us = <150>;
86 exit-latency-us = <200>;
87 min-residency-us = <2000>;
94 reg = <0x0 0x0>;
99 compatible = "qcom,scm-apq8084", "qcom,scm";
101 clock-names = "core", "bus", "iface";
105 thermal-zones {
106 cpu0-thermal {
107 polling-delay-passive = <250>;
108 polling-delay = <1000>;
110 thermal-sensors = <&tsens 5>;
126 cpu1-thermal {
127 polling-delay-passive = <250>;
128 polling-delay = <1000>;
130 thermal-sensors = <&tsens 6>;
146 cpu2-thermal {
147 polling-delay-passive = <250>;
148 polling-delay = <1000>;
150 thermal-sensors = <&tsens 7>;
166 cpu3-thermal {
167 polling-delay-passive = <250>;
168 polling-delay = <1000>;
170 thermal-sensors = <&tsens 8>;
187 cpu-pmu {
188 compatible = "qcom,krait-pmu";
189 interrupts = <GIC_PPI 7 0xf04>;
194 compatible = "fixed-clock";
195 #clock-cells = <0>;
196 clock-frequency = <19200000>;
200 compatible = "fixed-clock";
201 #clock-cells = <0>;
202 clock-frequency = <32768>;
207 compatible = "arm,armv7-timer";
208 interrupts = <GIC_PPI 2 0xf08>,
209 <GIC_PPI 3 0xf08>,
210 <GIC_PPI 4 0xf08>,
211 <GIC_PPI 1 0xf08>;
212 clock-frequency = <19200000>;
218 qcom,rpm-msg-ram = <&rpm_msg_ram>;
219 memory-region = <&smem_mem>;
225 #address-cells = <1>;
226 #size-cells = <1>;
228 compatible = "simple-bus";
230 intc: interrupt-controller@f9000000 {
231 compatible = "qcom,msm-qgic2";
232 interrupt-controller;
233 #interrupt-cells = <3>;
234 reg = <0xf9000000 0x1000>,
235 <0xf9002000 0x1000>;
240 reg = <0xf9011000 0x1000>;
244 compatible = "qcom,apq8084-rpm-stats";
245 reg = <0xfc190000 0x10000>;
249 compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
250 reg = <0xfc4bc000 0x1000>;
251 #address-cells = <1>;
252 #size-cells = <1>;
255 reg = <0xd0 0x1>;
256 bits = <0 8>;
259 tsens_s0_p1: s0-p1@d1 {
260 reg = <0xd1 0x1>;
261 bits = <0 6>;
264 tsens_s1_p1: s1-p1@d2 {
265 reg = <0xd1 0x2>;
266 bits = <6 6>;
269 tsens_s2_p1: s2-p1@d2 {
270 reg = <0xd2 0x2>;
271 bits = <4 6>;
274 tsens_s3_p1: s3-p1@d3 {
275 reg = <0xd3 0x1>;
276 bits = <2 6>;
279 tsens_s4_p1: s4-p1@d4 {
280 reg = <0xd4 0x1>;
281 bits = <0 6>;
284 tsens_s5_p1: s5-p1@d4 {
285 reg = <0xd4 0x2>;
286 bits = <6 6>;
289 tsens_s6_p1: s6-p1@d5 {
290 reg = <0xd5 0x2>;
291 bits = <4 6>;
294 tsens_s7_p1: s7-p1@d6 {
295 reg = <0xd6 0x1>;
296 bits = <2 6>;
299 tsens_s8_p1: s8-p1@d7 {
300 reg = <0xd7 0x1>;
301 bits = <0 6>;
305 reg = <0xd7 0x1>;
306 bits = <6 2>;
309 tsens_s9_p1: s9-p1@d8 {
310 reg = <0xd8 0x1>;
311 bits = <0 6>;
314 tsens_s10_p1: s10-p1@d8 {
315 reg = <0xd8 0x2>;
316 bits = <6 6>;
320 reg = <0xd9 0x2>;
324 tsens_s0_p2: s0-p2@da {
325 reg = <0xda 0x2>;
326 bits = <4 6>;
329 tsens_s1_p2: s1-p2@db {
330 reg = <0xdb 0x1>;
331 bits = <2 6>;
334 tsens_s2_p2: s2-p2@dc {
335 reg = <0xdc 0x1>;
336 bits = <0 6>;
339 tsens_s3_p2: s3-p2@dc {
340 reg = <0xdc 0x2>;
341 bits = <6 6>;
344 tsens_s4_p2: s4-p2@dd {
345 reg = <0xdd 0x2>;
346 bits = <4 6>;
349 tsens_s5_p2: s5-p2@de {
350 reg = <0xde 0x2>;
351 bits = <2 6>;
354 tsens_s6_p2: s6-p2@df {
355 reg = <0xdf 0x1>;
356 bits = <0 6>;
359 tsens_s7_p2: s7-p2@e0 {
360 reg = <0xe0 0x1>;
361 bits = <0 6>;
364 tsens_s8_p2: s8-p2@e0 {
365 reg = <0xe0 0x2>;
366 bits = <6 6>;
369 tsens_s9_p2: s9-p2@e1 {
370 reg = <0xe1 0x2>;
371 bits = <4 6>;
374 tsens_s10_p2: s10-p2@e2 {
375 reg = <0xe2 0x2>;
376 bits = <2 6>;
379 tsens_s5_p2_backup: s5-p2-backup@e3 {
380 reg = <0xe3 0x2>;
381 bits = <0 6>;
384 tsens_mode_backup: mode-backup@e3 {
385 reg = <0xe3 0x1>;
386 bits = <6 2>;
389 tsens_s6_p2_backup: s6-p2-backup@e4 {
390 reg = <0xe4 0x1>;
391 bits = <0 6>;
394 tsens_s7_p2_backup: s7-p2-backup@e4 {
395 reg = <0xe4 0x2>;
396 bits = <6 6>;
399 tsens_s8_p2_backup: s8-p2-backup@e5 {
400 reg = <0xe5 0x2>;
401 bits = <4 6>;
404 tsens_s9_p2_backup: s9-p2-backup@e6 {
405 reg = <0xe6 0x2>;
406 bits = <2 6>;
409 tsens_s10_p2_backup: s10-p2-backup@e7 {
410 reg = <0xe7 0x1>;
411 bits = <0 6>;
414 tsens_base1_backup: base1-backup@440 {
415 reg = <0x440 0x1>;
416 bits = <0 8>;
419 tsens_s0_p1_backup: s0-p1-backup@441 {
420 reg = <0x441 0x1>;
421 bits = <0 6>;
424 tsens_s1_p1_backup: s1-p1-backup@442 {
425 reg = <0x441 0x2>;
426 bits = <6 6>;
429 tsens_s2_p1_backup: s2-p1-backup@442 {
430 reg = <0x442 0x2>;
431 bits = <4 6>;
434 tsens_s3_p1_backup: s3-p1-backup@443 {
435 reg = <0x443 0x1>;
436 bits = <2 6>;
439 tsens_s4_p1_backup: s4-p1-backup@444 {
440 reg = <0x444 0x1>;
441 bits = <0 6>;
444 tsens_s5_p1_backup: s5-p1-backup@444 {
445 reg = <0x444 0x2>;
446 bits = <6 6>;
449 tsens_s6_p1_backup: s6-p1-backup@445 {
450 reg = <0x445 0x2>;
451 bits = <4 6>;
454 tsens_s7_p1_backup: s7-p1-backup@446 {
455 reg = <0x446 0x1>;
456 bits = <2 6>;
459 tsens_use_backup: use-backup@447 {
460 reg = <0x447 0x1>;
464 tsens_s8_p1_backup: s8-p1-backup@448 {
465 reg = <0x448 0x1>;
466 bits = <0 6>;
469 tsens_s9_p1_backup: s9-p1-backup@448 {
470 reg = <0x448 0x2>;
471 bits = <6 6>;
474 tsens_s10_p1_backup: s10-p1-backup@449 {
475 reg = <0x449 0x2>;
476 bits = <4 6>;
479 tsens_base2_backup: base2-backup@44a {
480 reg = <0x44a 0x2>;
484 tsens_s0_p2_backup: s0-p2-backup@44b {
485 reg = <0x44b 0x3>;
486 bits = <2 6>;
489 tsens_s1_p2_backup: s1-p2-backup@44c {
490 reg = <0x44c 0x1>;
491 bits = <0 6>;
494 tsens_s2_p2_backup: s2-p2-backup@44c {
495 reg = <0x44c 0x2>;
496 bits = <6 6>;
499 tsens_s3_p2_backup: s3-p2-backup@44d {
500 reg = <0x44d 0x2>;
501 bits = <4 6>;
504 tsens_s4_p2_backup: s4-p2-backup@44e {
505 reg = <0x44e 0x1>;
506 bits = <2 6>;
510 tsens: thermal-sensor@fc4a9000 {
511 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
512 reg = <0xfc4a9000 0x1000>, /* TM */
513 <0xfc4a8000 0x1000>; /* SROT */
514 nvmem-cells = <&tsens_mode>,
541 nvmem-cell-names = "mode",
570 interrupt-names = "uplow";
571 #thermal-sensor-cells = <1>;
574 #address-cells = <1>;
575 #size-cells = <1>;
577 compatible = "arm,armv7-timer-mem";
578 reg = <0xf9020000 0x1000>;
579 clock-frequency = <19200000>;
582 frame-number = <0>;
585 reg = <0xf9021000 0x1000>,
586 <0xf9022000 0x1000>;
590 frame-number = <1>;
592 reg = <0xf9023000 0x1000>;
597 frame-number = <2>;
599 reg = <0xf9024000 0x1000>;
604 frame-number = <3>;
606 reg = <0xf9025000 0x1000>;
611 frame-number = <4>;
613 reg = <0xf9026000 0x1000>;
618 frame-number = <5>;
620 reg = <0xf9027000 0x1000>;
625 frame-number = <6>;
627 reg = <0xf9028000 0x1000>;
632 saw0: power-manager@f9089000 {
633 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
634 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
637 saw1: power-manager@f9099000 {
638 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
639 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
642 saw2: power-manager@f90a9000 {
643 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
644 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
647 saw3: power-manager@f90b9000 {
648 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
649 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
652 saw_l2: power-manager@f9012000 {
653 compatible = "qcom,apq8084-saw2-v2.1-l2", "qcom,saw2";
654 reg = <0xf9012000 0x1000>;
657 acc0: power-manager@f9088000 {
658 compatible = "qcom,kpss-acc-v2";
659 reg = <0xf9088000 0x1000>,
660 <0xf9008000 0x1000>;
663 acc1: power-manager@f9098000 {
664 compatible = "qcom,kpss-acc-v2";
665 reg = <0xf9098000 0x1000>,
666 <0xf9008000 0x1000>;
669 acc2: power-manager@f90a8000 {
670 compatible = "qcom,kpss-acc-v2";
671 reg = <0xf90a8000 0x1000>,
672 <0xf9008000 0x1000>;
675 acc3: power-manager@f90b8000 {
676 compatible = "qcom,kpss-acc-v2";
677 reg = <0xf90b8000 0x1000>,
678 <0xf9008000 0x1000>;
683 reg = <0xfc4ab000 0x4>;
686 gcc: clock-controller@fc400000 {
687 compatible = "qcom,gcc-apq8084";
688 #clock-cells = <1>;
689 #reset-cells = <1>;
690 #power-domain-cells = <1>;
691 reg = <0xfc400000 0x4000>;
694 <0>, /* ufs */
695 <0>,
696 <0>,
697 <0>,
698 <0>, /* sata */
699 <0>,
700 <0>; /* pcie */
701 clock-names = "xo",
713 compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex";
714 reg = <0xfd484000 0x1000>;
715 #hwlock-cells = <1>;
719 compatible = "qcom,rpm-msg-ram";
720 reg = <0xfc428000 0x4000>;
724 compatible = "qcom,apq8084-pinctrl";
725 reg = <0xfd510000 0x4000>;
726 gpio-controller;
727 gpio-ranges = <&tlmm 0 0 147>;
728 #gpio-cells = <2>;
729 interrupt-controller;
730 #interrupt-cells = <2>;
735 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
736 reg = <0xf995e000 0x1000>;
739 clock-names = "core", "iface";
744 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
745 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
746 reg-names = "hc", "core";
748 interrupt-names = "hc_irq", "pwr_irq";
752 clock-names = "iface", "core", "xo";
757 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
758 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
759 reg-names = "hc", "core";
761 interrupt-names = "hc_irq", "pwr_irq";
765 clock-names = "iface", "core", "xo";
770 compatible = "qcom,spmi-pmic-arb";
771 reg-names = "core", "intr", "cnfg";
772 reg = <0xfc4cf000 0x1000>,
773 <0xfc4cb000 0x1000>,
774 <0xfc4ca000 0x1000>;
775 interrupt-names = "periph_irq";
777 qcom,ee = <0>;
778 qcom,channel = <0>;
779 #address-cells = <2>;
780 #size-cells = <0>;
781 interrupt-controller;
782 #interrupt-cells = <4>;
787 compatible = "qcom,apq8084-rpm-proc", "qcom,rpm-proc";
789 smd-edge {
791 qcom,ipc = <&apcs 8 0>;
792 qcom,smd-edge = <15>;
794 rpm-requests {
795 compatible = "qcom,rpm-apq8084", "qcom,smd-rpm";
796 qcom,smd-channels = "rpm_requests";
798 regulators-0 {
799 compatible = "qcom,rpm-pma8084-regulators";