Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 interrupt-parent = <&intc>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
25 reg = <0x80000000 0x200000>;
26 no-map;
30 reg = <0x8f000000 0x700000>;
31 no-map;
36 #address-cells = <1>;
37 #size-cells = <0>;
41 enable-method = "qcom,kpss-acc-v1";
43 reg = <0>;
44 next-level-cache = <&l2>;
47 cpu-idle-states = <&cpu_spc>;
52 enable-method = "qcom,kpss-acc-v1";
54 reg = <1>;
55 next-level-cache = <&l2>;
58 cpu-idle-states = <&cpu_spc>;
63 enable-method = "qcom,kpss-acc-v1";
65 reg = <2>;
66 next-level-cache = <&l2>;
69 cpu-idle-states = <&cpu_spc>;
74 enable-method = "qcom,kpss-acc-v1";
76 reg = <3>;
77 next-level-cache = <&l2>;
80 cpu-idle-states = <&cpu_spc>;
83 l2: l2-cache {
85 cache-level = <2>;
86 cache-unified;
89 idle-states {
90 cpu_spc: cpu-spc {
91 compatible = "qcom,idle-state-spc",
92 "arm,idle-state";
93 entry-latency-us = <400>;
94 exit-latency-us = <900>;
95 min-residency-us = <3000>;
102 reg = <0x0 0x0>;
105 thermal-zones {
106 cpu0-thermal {
107 polling-delay-passive = <250>;
108 polling-delay = <1000>;
110 thermal-sensors = <&tsens 7>;
127 cpu1-thermal {
128 polling-delay-passive = <250>;
129 polling-delay = <1000>;
131 thermal-sensors = <&tsens 8>;
148 cpu2-thermal {
149 polling-delay-passive = <250>;
150 polling-delay = <1000>;
152 thermal-sensors = <&tsens 9>;
169 cpu3-thermal {
170 polling-delay-passive = <250>;
171 polling-delay = <1000>;
173 thermal-sensors = <&tsens 10>;
191 cpu-pmu {
192 compatible = "qcom,krait-pmu";
198 compatible = "fixed-clock";
199 #clock-cells = <0>;
200 clock-frequency = <19200000>;
204 compatible = "fixed-clock";
205 #clock-cells = <0>;
206 clock-frequency = <27000000>;
210 compatible = "fixed-clock";
211 #clock-cells = <0>;
212 clock-frequency = <32768>;
218 memory-region = <&smem_region>;
226 #address-cells = <1>;
227 #size-cells = <0>;
229 qcom,ipc-1 = <&l2cc 8 4>;
230 qcom,ipc-2 = <&l2cc 8 14>;
231 qcom,ipc-3 = <&l2cc 8 23>;
232 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
235 reg = <0>;
236 #qcom,smem-state-cells = <1>;
240 reg = <1>;
243 interrupt-controller;
244 #interrupt-cells = <2>;
248 reg = <2>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
256 reg = <3>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
264 reg = <4>;
267 interrupt-controller;
268 #interrupt-cells = <2>;
274 compatible = "qcom,scm-apq8064", "qcom,scm";
277 clock-names = "core";
282 compatible = "arm,coresight-static-replicator";
285 clock-names = "apb_pclk";
287 in-ports {
290 remote-endpoint = <&funnel_out>;
295 out-ports {
296 #address-cells = <1>;
297 #size-cells = <0>;
300 reg = <0>;
302 remote-endpoint = <&etb_in>;
307 reg = <1>;
309 remote-endpoint = <&tpiu_in>;
316 #address-cells = <1>;
317 #size-cells = <1>;
319 compatible = "simple-bus";
322 compatible = "qcom,apq8064-pinctrl";
323 reg = <0x800000 0x4000>;
325 gpio-controller;
326 gpio-ranges = <&tlmm_pinmux 0 0 90>;
327 #gpio-cells = <2>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&ps_hold_default_state>;
337 compatible = "qcom,sfpb-mutex";
338 reg = <0x01200600 0x100>;
339 #hwlock-cells = <1>;
342 intc: interrupt-controller@2000000 {
343 compatible = "qcom,msm-qgic2";
344 interrupt-controller;
345 #interrupt-cells = <3>;
346 reg = <0x02000000 0x1000>,
351 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
352 "qcom,msm-timer";
356 reg = <0x0200a000 0x100>;
357 clock-frequency = <27000000>;
359 clock-names = "sleep";
360 cpu-offset = <0x80000>;
363 acc0: clock-controller@2088000 {
364 compatible = "qcom,kpss-acc-v1";
365 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
367 clock-names = "pll8_vote", "pxo";
368 clock-output-names = "acpu0_aux";
369 #clock-cells = <0>;
372 acc1: clock-controller@2098000 {
373 compatible = "qcom,kpss-acc-v1";
374 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
376 clock-names = "pll8_vote", "pxo";
377 clock-output-names = "acpu1_aux";
378 #clock-cells = <0>;
381 acc2: clock-controller@20a8000 {
382 compatible = "qcom,kpss-acc-v1";
383 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
385 clock-names = "pll8_vote", "pxo";
386 clock-output-names = "acpu2_aux";
387 #clock-cells = <0>;
390 acc3: clock-controller@20b8000 {
391 compatible = "qcom,kpss-acc-v1";
392 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
394 clock-names = "pll8_vote", "pxo";
395 clock-output-names = "acpu3_aux";
396 #clock-cells = <0>;
399 saw0: power-manager@2089000 {
400 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
401 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
404 regulator-min-microvolt = <850000>;
405 regulator-max-microvolt = <1300000>;
409 saw1: power-manager@2099000 {
410 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
411 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
414 regulator-min-microvolt = <850000>;
415 regulator-max-microvolt = <1300000>;
419 saw2: power-manager@20a9000 {
420 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
421 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
424 regulator-min-microvolt = <850000>;
425 regulator-max-microvolt = <1300000>;
429 saw3: power-manager@20b9000 {
430 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
431 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
434 regulator-min-microvolt = <850000>;
435 regulator-max-microvolt = <1300000>;
439 sps_sic_non_secure: interrupt-controller@12100000 {
440 compatible = "qcom,apq8064-sps-sic", "syscon";
441 reg = <0x12100000 0x10000>;
446 compatible = "qcom,gsbi-v1.0.0";
447 cell-index = <1>;
448 reg = <0x12440000 0x100>;
450 clock-names = "iface";
451 #address-cells = <1>;
452 #size-cells = <1>;
455 syscon-tcsr = <&tcsr>;
458 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
459 reg = <0x12450000 0x100>,
463 clock-names = "core", "iface";
468 compatible = "qcom,i2c-qup-v1.1.1";
469 pinctrl-0 = <&i2c1_default_state>;
470 pinctrl-1 = <&i2c1_sleep_state>;
471 pinctrl-names = "default", "sleep";
472 reg = <0x12460000 0x1000>;
475 clock-names = "core", "iface";
476 #address-cells = <1>;
477 #size-cells = <0>;
485 compatible = "qcom,gsbi-v1.0.0";
486 cell-index = <2>;
487 reg = <0x12480000 0x100>;
489 clock-names = "iface";
490 #address-cells = <1>;
491 #size-cells = <1>;
494 syscon-tcsr = <&tcsr>;
497 compatible = "qcom,i2c-qup-v1.1.1";
498 reg = <0x124a0000 0x1000>;
499 pinctrl-0 = <&i2c2_default_state>;
500 pinctrl-1 = <&i2c2_sleep_state>;
501 pinctrl-names = "default", "sleep";
504 clock-names = "core", "iface";
505 #address-cells = <1>;
506 #size-cells = <0>;
513 compatible = "qcom,gsbi-v1.0.0";
514 cell-index = <3>;
515 reg = <0x16200000 0x100>;
517 clock-names = "iface";
518 #address-cells = <1>;
519 #size-cells = <1>;
522 compatible = "qcom,i2c-qup-v1.1.1";
523 pinctrl-0 = <&i2c3_default_state>;
524 pinctrl-1 = <&i2c3_sleep_state>;
525 pinctrl-names = "default", "sleep";
526 reg = <0x16280000 0x1000>;
530 clock-names = "core", "iface";
531 #address-cells = <1>;
532 #size-cells = <0>;
539 compatible = "qcom,gsbi-v1.0.0";
540 cell-index = <4>;
541 reg = <0x16300000 0x03>;
543 clock-names = "iface";
544 #address-cells = <1>;
545 #size-cells = <1>;
549 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
550 reg = <0x16340000 0x100>,
553 pinctrl-0 = <&gsbi4_uart_pin_a>;
554 pinctrl-names = "default";
556 clock-names = "core", "iface";
561 compatible = "qcom,i2c-qup-v1.1.1";
562 pinctrl-0 = <&i2c4_default_state>;
563 pinctrl-1 = <&i2c4_sleep_state>;
564 pinctrl-names = "default", "sleep";
565 reg = <0x16380000 0x1000>;
569 clock-names = "core", "iface";
576 compatible = "qcom,gsbi-v1.0.0";
577 cell-index = <5>;
578 reg = <0x1a200000 0x03>;
580 clock-names = "iface";
581 #address-cells = <1>;
582 #size-cells = <1>;
586 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
587 reg = <0x1a240000 0x100>,
591 clock-names = "core", "iface";
596 compatible = "qcom,spi-qup-v1.1.1";
597 reg = <0x1a280000 0x1000>;
599 pinctrl-0 = <&spi5_default_state>;
600 pinctrl-1 = <&spi5_sleep_state>;
601 pinctrl-names = "default", "sleep";
603 clock-names = "core", "iface";
605 #address-cells = <1>;
606 #size-cells = <0>;
612 compatible = "qcom,gsbi-v1.0.0";
613 cell-index = <6>;
614 reg = <0x16500000 0x03>;
616 clock-names = "iface";
617 #address-cells = <1>;
618 #size-cells = <1>;
622 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
623 reg = <0x16540000 0x100>,
627 clock-names = "core", "iface";
632 compatible = "qcom,i2c-qup-v1.1.1";
633 pinctrl-0 = <&i2c6_default_state>;
634 pinctrl-1 = <&i2c6_sleep_state>;
635 pinctrl-names = "default", "sleep";
636 reg = <0x16580000 0x1000>;
640 clock-names = "core", "iface";
647 compatible = "qcom,gsbi-v1.0.0";
648 cell-index = <7>;
649 reg = <0x16600000 0x100>;
651 clock-names = "iface";
652 #address-cells = <1>;
653 #size-cells = <1>;
655 syscon-tcsr = <&tcsr>;
658 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
659 reg = <0x16640000 0x1000>,
663 clock-names = "core", "iface";
668 compatible = "qcom,i2c-qup-v1.1.1";
669 pinctrl-0 = <&i2c7_default_state>;
670 pinctrl-1 = <&i2c7_sleep_state>;
671 pinctrl-names = "default", "sleep";
672 reg = <0x16680000 0x1000>;
676 clock-names = "core", "iface";
683 reg = <0x1a500000 0x200>;
685 clock-names = "core";
690 reg = <0x00c00000 0x1000>;
691 qcom,controller-type = "pmic-arbiter";
696 reg = <0x00500000 0x1000>;
697 qcom,controller-type = "pmic-arbiter";
701 compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
702 reg = <0x00700000 0x1000>;
703 #address-cells = <1>;
704 #size-cells = <1>;
707 reg = <0x404 0x10>;
709 tsens_backup: backup-calib@414 {
710 reg = <0x414 0x10>;
714 gcc: clock-controller@900000 {
715 compatible = "qcom,gcc-apq8064", "syscon";
716 reg = <0x00900000 0x4000>;
717 #clock-cells = <1>;
718 #reset-cells = <1>;
722 clock-names = "cxo", "pxo", "pll4";
724 tsens: thermal-sensor {
725 compatible = "qcom,msm8960-tsens";
727 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
728 nvmem-cell-names = "calib", "calib_backup";
730 interrupt-names = "uplow";
733 #thermal-sensor-cells = <1>;
737 lcc: clock-controller@28000000 {
738 compatible = "qcom,lcc-apq8064";
739 reg = <0x28000000 0x1000>;
740 #clock-cells = <1>;
741 #reset-cells = <1>;
748 clock-names = "pxo",
758 mmcc: clock-controller@4000000 {
759 compatible = "qcom,mmcc-apq8064";
760 reg = <0x4000000 0x1000>;
761 #clock-cells = <1>;
762 #power-domain-cells = <1>;
763 #reset-cells = <1>;
773 clock-names = "pxo",
784 l2cc: clock-controller@2011000 {
785 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
786 reg = <0x2011000 0x1000>;
788 clock-names = "pll8_vote", "pxo";
789 #clock-cells = <0>;
793 compatible = "qcom,rpm-apq8064";
794 reg = <0x108000 0x1000>;
800 interrupt-names = "ack", "err", "wakeup";
802 rpmcc: clock-controller {
803 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
804 #clock-cells = <1>;
806 clock-names = "pxo", "cxo";
811 compatible = "qcom,ci-hdrc";
812 reg = <0x12500000 0x200>,
816 clock-names = "core", "iface";
817 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
818 assigned-clock-rates = <60000000>;
820 reset-names = "core";
822 ahb-burst-config = <0>;
824 phy-names = "usb-phy";
826 #reset-cells = <1>;
830 compatible = "qcom,usb-hs-phy-apq8064",
831 "qcom,usb-hs-phy";
833 clock-names = "sleep", "ref";
835 reset-names = "por";
836 #phy-cells = <0>;
842 compatible = "qcom,ci-hdrc";
843 reg = <0x12520000 0x200>,
847 clock-names = "core", "iface";
848 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
849 assigned-clock-rates = <60000000>;
851 reset-names = "core";
853 ahb-burst-config = <0>;
855 phy-names = "usb-phy";
857 #reset-cells = <1>;
861 compatible = "qcom,usb-hs-phy-apq8064",
862 "qcom,usb-hs-phy";
863 #phy-cells = <0>;
865 clock-names = "sleep", "ref";
867 reset-names = "por";
873 compatible = "qcom,ci-hdrc";
874 reg = <0x12530000 0x200>,
878 clock-names = "core", "iface";
879 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
880 assigned-clock-rates = <60000000>;
882 reset-names = "core";
884 ahb-burst-config = <0>;
886 phy-names = "usb-phy";
888 #reset-cells = <1>;
892 compatible = "qcom,usb-hs-phy-apq8064",
893 "qcom,usb-hs-phy";
894 #phy-cells = <0>;
896 clock-names = "sleep", "ref";
898 reset-names = "por";
904 compatible = "qcom,apq8064-sata-phy";
906 reg = <0x1b400000 0x200>;
908 clock-names = "cfg";
909 #phy-cells = <0>;
913 compatible = "qcom,apq8064-ahci", "generic-ahci";
915 reg = <0x29000000 0x180>;
923 clock-names = "slave_iface",
929 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
931 assigned-clock-rates = <100000000>, <100000000>;
934 phy-names = "sata-phy";
935 ports-implemented = <0x1>;
940 arm,primecell-periphid = <0x00051180>;
942 reg = <0x12180000 0x2000>;
945 clock-names = "mclk", "apb_pclk";
946 bus-width = <4>;
947 cap-sd-highspeed;
948 cap-mmc-highspeed;
949 max-frequency = <192000000>;
950 no-1-8-v;
952 dma-names = "tx", "rx";
955 sdcc3bam: dma-controller@12182000 {
956 compatible = "qcom,bam-v1.3.0";
957 reg = <0x12182000 0x8000>;
960 clock-names = "bam_clk";
961 #dma-cells = <1>;
967 arm,primecell-periphid = <0x00051180>;
969 reg = <0x121c0000 0x2000>;
972 clock-names = "mclk", "apb_pclk";
973 bus-width = <4>;
974 cap-sd-highspeed;
975 cap-mmc-highspeed;
976 max-frequency = <48000000>;
978 dma-names = "tx", "rx";
979 pinctrl-names = "default";
980 pinctrl-0 = <&sdc4_default_state>;
983 sdcc4bam: dma-controller@121c2000 {
984 compatible = "qcom,bam-v1.3.0";
985 reg = <0x121c2000 0x8000>;
988 clock-names = "bam_clk";
989 #dma-cells = <1>;
996 pinctrl-names = "default";
997 pinctrl-0 = <&sdcc1_default_state>;
998 arm,primecell-periphid = <0x00051180>;
999 reg = <0x12400000 0x2000>;
1002 clock-names = "mclk", "apb_pclk";
1003 bus-width = <8>;
1004 max-frequency = <96000000>;
1005 non-removable;
1006 cap-sd-highspeed;
1007 cap-mmc-highspeed;
1009 dma-names = "tx", "rx";
1012 sdcc1bam: dma-controller@12402000 {
1013 compatible = "qcom,bam-v1.3.0";
1014 reg = <0x12402000 0x8000>;
1017 clock-names = "bam_clk";
1018 #dma-cells = <1>;
1023 compatible = "qcom,tcsr-apq8064", "syscon";
1024 reg = <0x1a400000 0x100>;
1028 compatible = "qcom,adreno-320.2", "qcom,adreno";
1029 reg = <0x04300000 0x20000>;
1030 reg-names = "kgsl_3d0_reg_memory";
1032 interrupt-names = "kgsl_3d0_irq";
1033 clock-names =
1109 operating-points-v2 = <&gpu_opp_table>;
1111 gpu_opp_table: opp-table {
1112 compatible = "operating-points-v2";
1114 opp-450000000 {
1115 opp-hz = /bits/ 64 <450000000>;
1118 opp-27000000 {
1119 opp-hz = /bits/ 64 <27000000>;
1125 compatible = "qcom,apq8064-mmss-sfpb", "syscon";
1126 reg = <0x5700000 0x70>;
1130 compatible = "qcom,apq8064-dsi-ctrl",
1131 "qcom,mdss-dsi-ctrl";
1132 #address-cells = <1>;
1133 #size-cells = <0>;
1135 reg = <0x04700000 0x200>;
1136 reg-names = "dsi_ctrl";
1145 clock-names = "iface", "bus", "core_mmss",
1149 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1153 assigned-clock-parents = <&dsi0_phy 0>,
1157 syscon-sfpb = <&mmss_sfpb>;
1162 #address-cells = <1>;
1163 #size-cells = <0>;
1166 reg = <0>;
1172 reg = <1>;
1181 compatible = "qcom,dsi-phy-28nm-8960";
1182 #clock-cells = <1>;
1183 #phy-cells = <0>;
1185 reg = <0x04700200 0x100>,
1188 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1189 clock-names = "iface", "ref";
1196 compatible = "qcom,mdss-dsi-ctrl";
1198 reg = <0x05800000 0x200>;
1199 reg-names = "dsi_ctrl";
1208 clock-names = "iface",
1216 assigned-clocks = <&mmcc DSI2_BYTE_SRC>,
1220 assigned-clock-parents = <&dsi1_phy 0>,
1225 syscon-sfpb = <&mmss_sfpb>;
1228 #address-cells = <1>;
1229 #size-cells = <0>;
1234 #address-cells = <1>;
1235 #size-cells = <0>;
1238 reg = <0>;
1244 reg = <1>;
1252 dsi1_phy: dsi-phy@5800200 {
1253 compatible = "qcom,dsi-phy-28nm-8960";
1254 reg = <0x05800200 0x100>,
1257 reg-names = "dsi_pll",
1260 clock-names = "iface",
1264 #clock-cells = <1>;
1265 #phy-cells = <0>;
1271 compatible = "qcom,apq8064-iommu";
1272 #iommu-cells = <1>;
1273 clock-names =
1279 reg = <0x07500000 0x100000>;
1287 compatible = "qcom,apq8064-iommu";
1288 #iommu-cells = <1>;
1289 clock-names =
1295 reg = <0x07600000 0x100000>;
1303 compatible = "qcom,apq8064-iommu";
1304 #iommu-cells = <1>;
1305 clock-names =
1311 reg = <0x07c00000 0x100000>;
1319 compatible = "qcom,apq8064-iommu";
1320 #iommu-cells = <1>;
1321 clock-names =
1327 reg = <0x07d00000 0x100000>;
1335 compatible = "qcom,pcie-apq8064";
1336 reg = <0x1b500000 0x1000>,
1340 reg-names = "dbi", "elbi", "parf", "config";
1342 linux,pci-domain = <0>;
1343 bus-range = <0x00 0xff>;
1344 num-lanes = <1>;
1345 #address-cells = <3>;
1346 #size-cells = <2>;
1350 interrupt-names = "msi";
1351 #interrupt-cells = <1>;
1352 interrupt-map-mask = <0 0 0 0x7>;
1353 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1360 clock-names = "core", "iface", "phy";
1366 reset-names = "axi", "ahb", "por", "pci", "phy";
1371 reg = <0x0 0x0 0x0 0x0 0x0>;
1372 bus-range = <0x01 0xff>;
1374 #address-cells = <3>;
1375 #size-cells = <2>;
1380 hdmi: hdmi-tx@4a00000 {
1381 compatible = "qcom,hdmi-tx-8960";
1382 pinctrl-names = "default";
1383 pinctrl-0 = <&hdmi_pinctrl>;
1384 reg = <0x04a00000 0x2f0>;
1385 reg-names = "core_physical";
1390 clock-names = "core",
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1403 reg = <0>;
1409 reg = <1>;
1417 compatible = "qcom,hdmi-phy-8960";
1418 reg = <0x4a00400 0x60>,
1420 reg-names = "hdmi_phy",
1424 clock-names = "slave_iface";
1425 #phy-cells = <0>;
1426 #clock-cells = <0>;
1431 mdp: display-controller@5100000 {
1433 reg = <0x05100000 0xf0000>;
1443 clock-names = "core_clk",
1452 #clock-cells = <0>;
1460 #address-cells = <1>;
1461 #size-cells = <0>;
1464 reg = <0>;
1470 reg = <1>;
1476 reg = <2>;
1482 reg = <3>;
1489 riva: riva-pil@3200800 {
1490 compatible = "qcom,riva-pil";
1492 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1493 reg-names = "ccu", "dxe", "pmu";
1495 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1497 interrupt-names = "wdog", "fatal";
1499 memory-region = <&wcnss_mem>;
1507 clock-names = "xo";
1510 smd-edge {
1514 qcom,smd-edge = <6>;
1520 qcom,smd-channels = "WCNSS_CTRL";
1525 compatible = "qcom,wcnss-bt";
1529 compatible = "qcom,wcnss-wlan";
1533 interrupt-names = "tx", "rx";
1535 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1536 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1543 compatible = "arm,coresight-etb10", "arm,primecell";
1544 reg = <0x1a01000 0x1000>;
1547 clock-names = "apb_pclk";
1549 in-ports {
1552 remote-endpoint = <&replicator_out0>;
1559 compatible = "arm,coresight-tpiu", "arm,primecell";
1560 reg = <0x1a03000 0x1000>;
1563 clock-names = "apb_pclk";
1565 in-ports {
1568 remote-endpoint = <&replicator_out1>;
1575 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1576 reg = <0x1a04000 0x1000>;
1579 clock-names = "apb_pclk";
1581 in-ports {
1582 #address-cells = <1>;
1583 #size-cells = <0>;
1587 * 2 - connected to STM component
1588 * 3 - not-connected
1589 * 6 - not-connected
1590 * 7 - not-connected
1593 reg = <0>;
1595 remote-endpoint = <&etm0_out>;
1599 reg = <1>;
1601 remote-endpoint = <&etm1_out>;
1605 reg = <4>;
1607 remote-endpoint = <&etm2_out>;
1611 reg = <5>;
1613 remote-endpoint = <&etm3_out>;
1618 out-ports {
1621 remote-endpoint = <&replicator_in>;
1628 compatible = "arm,coresight-etm3x", "arm,primecell";
1629 reg = <0x1a1c000 0x1000>;
1632 clock-names = "apb_pclk";
1636 out-ports {
1639 remote-endpoint = <&funnel_in0>;
1646 compatible = "arm,coresight-etm3x", "arm,primecell";
1647 reg = <0x1a1d000 0x1000>;
1650 clock-names = "apb_pclk";
1654 out-ports {
1657 remote-endpoint = <&funnel_in1>;
1664 compatible = "arm,coresight-etm3x", "arm,primecell";
1665 reg = <0x1a1e000 0x1000>;
1668 clock-names = "apb_pclk";
1672 out-ports {
1675 remote-endpoint = <&funnel_in4>;
1682 compatible = "arm,coresight-etm3x", "arm,primecell";
1683 reg = <0x1a1f000 0x1000>;
1686 clock-names = "apb_pclk";
1690 out-ports {
1693 remote-endpoint = <&funnel_in5>;
1700 #include "qcom-apq8064-pins.dtsi"