Lines Matching +full:bam +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 interrupt-parent = <&intc>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
26 no-map;
31 no-map;
36 #address-cells = <1>;
37 #size-cells = <0>;
41 enable-method = "qcom,kpss-acc-v1";
44 next-level-cache = <&L2>;
47 cpu-idle-states = <&CPU_SPC>;
52 enable-method = "qcom,kpss-acc-v1";
55 next-level-cache = <&L2>;
58 cpu-idle-states = <&CPU_SPC>;
63 enable-method = "qcom,kpss-acc-v1";
66 next-level-cache = <&L2>;
69 cpu-idle-states = <&CPU_SPC>;
74 enable-method = "qcom,kpss-acc-v1";
77 next-level-cache = <&L2>;
80 cpu-idle-states = <&CPU_SPC>;
83 L2: l2-cache {
85 cache-level = <2>;
86 cache-unified;
89 idle-states {
90 CPU_SPC: cpu-spc {
91 compatible = "qcom,idle-state-spc",
92 "arm,idle-state";
93 entry-latency-us = <400>;
94 exit-latency-us = <900>;
95 min-residency-us = <3000>;
105 thermal-zones {
106 cpu0-thermal {
107 polling-delay-passive = <250>;
108 polling-delay = <1000>;
110 thermal-sensors = <&tsens 7>;
127 cpu1-thermal {
128 polling-delay-passive = <250>;
129 polling-delay = <1000>;
131 thermal-sensors = <&tsens 8>;
148 cpu2-thermal {
149 polling-delay-passive = <250>;
150 polling-delay = <1000>;
152 thermal-sensors = <&tsens 9>;
169 cpu3-thermal {
170 polling-delay-passive = <250>;
171 polling-delay = <1000>;
173 thermal-sensors = <&tsens 10>;
191 cpu-pmu {
192 compatible = "qcom,krait-pmu";
198 compatible = "fixed-clock";
199 #clock-cells = <0>;
200 clock-frequency = <19200000>;
204 compatible = "fixed-clock";
205 #clock-cells = <0>;
206 clock-frequency = <27000000>;
210 compatible = "fixed-clock";
211 #clock-cells = <0>;
212 clock-frequency = <32768>;
217 compatible = "qcom,sfpb-mutex";
219 #hwlock-cells = <1>;
224 memory-region = <&smem_region>;
232 #address-cells = <1>;
233 #size-cells = <0>;
235 qcom,ipc-1 = <&l2cc 8 4>;
236 qcom,ipc-2 = <&l2cc 8 14>;
237 qcom,ipc-3 = <&l2cc 8 23>;
238 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
242 #qcom,smem-state-cells = <1>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
280 compatible = "qcom,scm-apq8064", "qcom,scm";
283 clock-names = "core";
288 #address-cells = <1>;
289 #size-cells = <1>;
291 compatible = "simple-bus";
294 compatible = "qcom,apq8064-pinctrl";
297 gpio-controller;
298 gpio-ranges = <&tlmm_pinmux 0 0 90>;
299 #gpio-cells = <2>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&ps_hold_default_state>;
313 intc: interrupt-controller@2000000 {
314 compatible = "qcom,msm-qgic2";
315 interrupt-controller;
316 #interrupt-cells = <3>;
322 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
323 "qcom,msm-timer";
328 clock-frequency = <27000000>;
329 cpu-offset = <0x80000>;
332 acc0: clock-controller@2088000 {
333 compatible = "qcom,kpss-acc-v1";
336 clock-names = "pll8_vote", "pxo";
337 clock-output-names = "acpu0_aux";
338 #clock-cells = <0>;
341 acc1: clock-controller@2098000 {
342 compatible = "qcom,kpss-acc-v1";
345 clock-names = "pll8_vote", "pxo";
346 clock-output-names = "acpu1_aux";
347 #clock-cells = <0>;
350 acc2: clock-controller@20a8000 {
351 compatible = "qcom,kpss-acc-v1";
354 clock-names = "pll8_vote", "pxo";
355 clock-output-names = "acpu2_aux";
356 #clock-cells = <0>;
359 acc3: clock-controller@20b8000 {
360 compatible = "qcom,kpss-acc-v1";
363 clock-names = "pll8_vote", "pxo";
364 clock-output-names = "acpu3_aux";
365 #clock-cells = <0>;
368 saw0: power-manager@2089000 {
369 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
373 regulator-min-microvolt = <850000>;
374 regulator-max-microvolt = <1300000>;
378 saw1: power-manager@2099000 {
379 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
383 regulator-min-microvolt = <850000>;
384 regulator-max-microvolt = <1300000>;
388 saw2: power-manager@20a9000 {
389 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
393 regulator-min-microvolt = <850000>;
394 regulator-max-microvolt = <1300000>;
398 saw3: power-manager@20b9000 {
399 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
403 regulator-min-microvolt = <850000>;
404 regulator-max-microvolt = <1300000>;
408 sps_sic_non_secure: sps-sic-non-secure@12100000 {
415 compatible = "qcom,gsbi-v1.0.0";
416 cell-index = <1>;
419 clock-names = "iface";
420 #address-cells = <1>;
421 #size-cells = <1>;
424 syscon-tcsr = <&tcsr>;
427 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
432 clock-names = "core", "iface";
437 compatible = "qcom,i2c-qup-v1.1.1";
438 pinctrl-0 = <&i2c1_default_state>;
439 pinctrl-1 = <&i2c1_sleep_state>;
440 pinctrl-names = "default", "sleep";
444 clock-names = "core", "iface";
445 #address-cells = <1>;
446 #size-cells = <0>;
454 compatible = "qcom,gsbi-v1.0.0";
455 cell-index = <2>;
458 clock-names = "iface";
459 #address-cells = <1>;
460 #size-cells = <1>;
463 syscon-tcsr = <&tcsr>;
466 compatible = "qcom,i2c-qup-v1.1.1";
468 pinctrl-0 = <&i2c2_default_state>;
469 pinctrl-1 = <&i2c2_sleep_state>;
470 pinctrl-names = "default", "sleep";
473 clock-names = "core", "iface";
474 #address-cells = <1>;
475 #size-cells = <0>;
482 compatible = "qcom,gsbi-v1.0.0";
483 cell-index = <3>;
486 clock-names = "iface";
487 #address-cells = <1>;
488 #size-cells = <1>;
491 compatible = "qcom,i2c-qup-v1.1.1";
492 pinctrl-0 = <&i2c3_default_state>;
493 pinctrl-1 = <&i2c3_sleep_state>;
494 pinctrl-names = "default", "sleep";
499 clock-names = "core", "iface";
500 #address-cells = <1>;
501 #size-cells = <0>;
508 compatible = "qcom,gsbi-v1.0.0";
509 cell-index = <4>;
512 clock-names = "iface";
513 #address-cells = <1>;
514 #size-cells = <1>;
518 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
522 pinctrl-0 = <&gsbi4_uart_pin_a>;
523 pinctrl-names = "default";
525 clock-names = "core", "iface";
530 compatible = "qcom,i2c-qup-v1.1.1";
531 pinctrl-0 = <&i2c4_default_state>;
532 pinctrl-1 = <&i2c4_sleep_state>;
533 pinctrl-names = "default", "sleep";
538 clock-names = "core", "iface";
545 compatible = "qcom,gsbi-v1.0.0";
546 cell-index = <5>;
549 clock-names = "iface";
550 #address-cells = <1>;
551 #size-cells = <1>;
555 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
560 clock-names = "core", "iface";
565 compatible = "qcom,spi-qup-v1.1.1";
568 pinctrl-0 = <&spi5_default_state>;
569 pinctrl-1 = <&spi5_sleep_state>;
570 pinctrl-names = "default", "sleep";
572 clock-names = "core", "iface";
574 #address-cells = <1>;
575 #size-cells = <0>;
581 compatible = "qcom,gsbi-v1.0.0";
582 cell-index = <6>;
585 clock-names = "iface";
586 #address-cells = <1>;
587 #size-cells = <1>;
591 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
596 clock-names = "core", "iface";
601 compatible = "qcom,i2c-qup-v1.1.1";
602 pinctrl-0 = <&i2c6_default_state>;
603 pinctrl-1 = <&i2c6_sleep_state>;
604 pinctrl-names = "default", "sleep";
609 clock-names = "core", "iface";
616 compatible = "qcom,gsbi-v1.0.0";
617 cell-index = <7>;
620 clock-names = "iface";
621 #address-cells = <1>;
622 #size-cells = <1>;
624 syscon-tcsr = <&tcsr>;
627 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
632 clock-names = "core", "iface";
637 compatible = "qcom,i2c-qup-v1.1.1";
638 pinctrl-0 = <&i2c7_default_state>;
639 pinctrl-1 = <&i2c7_sleep_state>;
640 pinctrl-names = "default", "sleep";
645 clock-names = "core", "iface";
654 clock-names = "core";
660 qcom,controller-type = "pmic-arbiter";
666 qcom,controller-type = "pmic-arbiter";
670 compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
672 #address-cells = <1>;
673 #size-cells = <1>;
683 gcc: clock-controller@900000 {
684 compatible = "qcom,gcc-apq8064", "syscon";
686 #clock-cells = <1>;
687 #reset-cells = <1>;
691 clock-names = "cxo", "pxo", "pll4";
693 tsens: thermal-sensor {
694 compatible = "qcom,msm8960-tsens";
696 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
697 nvmem-cell-names = "calib", "calib_backup";
699 interrupt-names = "uplow";
702 #thermal-sensor-cells = <1>;
706 lcc: clock-controller@28000000 {
707 compatible = "qcom,lcc-apq8064";
709 #clock-cells = <1>;
710 #reset-cells = <1>;
717 clock-names = "pxo",
727 mmcc: clock-controller@4000000 {
728 compatible = "qcom,mmcc-apq8064";
730 #clock-cells = <1>;
731 #power-domain-cells = <1>;
732 #reset-cells = <1>;
741 clock-names = "pxo",
751 l2cc: clock-controller@2011000 {
752 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
755 clock-names = "pll8_vote", "pxo";
756 #clock-cells = <0>;
760 compatible = "qcom,rpm-apq8064";
767 interrupt-names = "ack", "err", "wakeup";
769 rpmcc: clock-controller {
770 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
771 #clock-cells = <1>;
773 clock-names = "pxo", "cxo";
778 compatible = "qcom,ci-hdrc";
783 clock-names = "core", "iface";
784 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
785 assigned-clock-rates = <60000000>;
787 reset-names = "core";
789 ahb-burst-config = <0>;
791 phy-names = "usb-phy";
793 #reset-cells = <1>;
797 compatible = "qcom,usb-hs-phy-apq8064",
798 "qcom,usb-hs-phy";
800 clock-names = "sleep", "ref";
802 reset-names = "por";
803 #phy-cells = <0>;
809 compatible = "qcom,ci-hdrc";
814 clock-names = "core", "iface";
815 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
816 assigned-clock-rates = <60000000>;
818 reset-names = "core";
820 ahb-burst-config = <0>;
822 phy-names = "usb-phy";
824 #reset-cells = <1>;
828 compatible = "qcom,usb-hs-phy-apq8064",
829 "qcom,usb-hs-phy";
830 #phy-cells = <0>;
832 clock-names = "sleep", "ref";
834 reset-names = "por";
840 compatible = "qcom,ci-hdrc";
845 clock-names = "core", "iface";
846 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
847 assigned-clock-rates = <60000000>;
849 reset-names = "core";
851 ahb-burst-config = <0>;
853 phy-names = "usb-phy";
855 #reset-cells = <1>;
859 compatible = "qcom,usb-hs-phy-apq8064",
860 "qcom,usb-hs-phy";
861 #phy-cells = <0>;
863 clock-names = "sleep", "ref";
865 reset-names = "por";
871 compatible = "qcom,apq8064-sata-phy";
875 clock-names = "cfg";
876 #phy-cells = <0>;
880 compatible = "qcom,apq8064-ahci", "generic-ahci";
890 clock-names = "slave_iface",
896 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
898 assigned-clock-rates = <100000000>, <100000000>;
901 phy-names = "sata-phy";
902 ports-implemented = <0x1>;
907 arm,primecell-periphid = <0x00051180>;
912 clock-names = "mclk", "apb_pclk";
913 bus-width = <4>;
914 cap-sd-highspeed;
915 cap-mmc-highspeed;
916 max-frequency = <192000000>;
917 no-1-8-v;
919 dma-names = "tx", "rx";
922 sdcc3bam: dma-controller@12182000 {
923 compatible = "qcom,bam-v1.3.0";
927 clock-names = "bam_clk";
928 #dma-cells = <1>;
934 arm,primecell-periphid = <0x00051180>;
939 clock-names = "mclk", "apb_pclk";
940 bus-width = <4>;
941 cap-sd-highspeed;
942 cap-mmc-highspeed;
943 max-frequency = <48000000>;
945 dma-names = "tx", "rx";
946 pinctrl-names = "default";
947 pinctrl-0 = <&sdc4_default_state>;
950 sdcc4bam: dma-controller@121c2000 {
951 compatible = "qcom,bam-v1.3.0";
955 clock-names = "bam_clk";
956 #dma-cells = <1>;
963 pinctrl-names = "default";
964 pinctrl-0 = <&sdcc1_default_state>;
965 arm,primecell-periphid = <0x00051180>;
969 clock-names = "mclk", "apb_pclk";
970 bus-width = <8>;
971 max-frequency = <96000000>;
972 non-removable;
973 cap-sd-highspeed;
974 cap-mmc-highspeed;
976 dma-names = "tx", "rx";
979 sdcc1bam: dma-controller@12402000 {
980 compatible = "qcom,bam-v1.3.0";
984 clock-names = "bam_clk";
985 #dma-cells = <1>;
990 compatible = "qcom,tcsr-apq8064", "syscon";
995 compatible = "qcom,adreno-320.2", "qcom,adreno";
997 reg-names = "kgsl_3d0_reg_memory";
999 interrupt-names = "kgsl_3d0_irq";
1000 clock-names =
1076 operating-points-v2 = <&gpu_opp_table>;
1078 gpu_opp_table: opp-table {
1079 compatible = "operating-points-v2";
1081 opp-450000000 {
1082 opp-hz = /bits/ 64 <450000000>;
1085 opp-27000000 {
1086 opp-hz = /bits/ 64 <27000000>;
1097 compatible = "qcom,apq8064-dsi-ctrl",
1098 "qcom,mdss-dsi-ctrl";
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1103 reg-names = "dsi_ctrl";
1112 clock-names = "iface", "bus", "core_mmss",
1116 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1120 assigned-clock-parents = <&dsi0_phy 0>,
1124 syscon-sfpb = <&mmss_sfpb>;
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1148 compatible = "qcom,dsi-phy-28nm-8960";
1149 #clock-cells = <1>;
1150 #phy-cells = <0>;
1155 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1156 clock-names = "iface", "ref";
1163 compatible = "qcom,mdss-dsi-ctrl";
1166 reg-names = "dsi_ctrl";
1175 clock-names = "iface",
1183 assigned-clocks = <&mmcc DSI2_BYTE_SRC>,
1187 assigned-clock-parents = <&dsi1_phy 0>,
1192 syscon-sfpb = <&mmss_sfpb>;
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1219 dsi1_phy: dsi-phy@5800200 {
1220 compatible = "qcom,dsi-phy-28nm-8960";
1224 reg-names = "dsi_pll",
1227 clock-names = "iface",
1231 #clock-cells = <1>;
1232 #phy-cells = <0>;
1238 compatible = "qcom,apq8064-iommu";
1239 #iommu-cells = <1>;
1240 clock-names =
1254 compatible = "qcom,apq8064-iommu";
1255 #iommu-cells = <1>;
1256 clock-names =
1270 compatible = "qcom,apq8064-iommu";
1271 #iommu-cells = <1>;
1272 clock-names =
1286 compatible = "qcom,apq8064-iommu";
1287 #iommu-cells = <1>;
1288 clock-names =
1302 compatible = "qcom,pcie-apq8064";
1307 reg-names = "dbi", "elbi", "parf", "config";
1309 linux,pci-domain = <0>;
1310 bus-range = <0x00 0xff>;
1311 num-lanes = <1>;
1312 #address-cells = <3>;
1313 #size-cells = <2>;
1317 interrupt-names = "msi";
1318 #interrupt-cells = <1>;
1319 interrupt-map-mask = <0 0 0 0x7>;
1320 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1327 clock-names = "core", "iface", "phy";
1333 reset-names = "axi", "ahb", "por", "pci", "phy";
1339 bus-range = <0x01 0xff>;
1341 #address-cells = <3>;
1342 #size-cells = <2>;
1347 hdmi: hdmi-tx@4a00000 {
1348 compatible = "qcom,hdmi-tx-8960";
1349 pinctrl-names = "default";
1350 pinctrl-0 = <&hdmi_pinctrl>;
1352 reg-names = "core_physical";
1357 clock-names = "core",
1366 #address-cells = <1>;
1367 #size-cells = <0>;
1384 compatible = "qcom,hdmi-phy-8960";
1387 reg-names = "hdmi_phy",
1391 clock-names = "slave_iface";
1392 #phy-cells = <0>;
1393 #clock-cells = <0>;
1398 mdp: display-controller@5100000 {
1408 clock-names = "core_clk",
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1450 riva: riva-pil@3200800 {
1451 compatible = "qcom,riva-pil";
1454 reg-names = "ccu", "dxe", "pmu";
1456 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1458 interrupt-names = "wdog", "fatal";
1460 memory-region = <&wcnss_mem>;
1468 clock-names = "xo";
1471 smd-edge {
1475 qcom,smd-edge = <6>;
1481 qcom,smd-channels = "WCNSS_CTRL";
1486 compatible = "qcom,wcnss-bt";
1490 compatible = "qcom,wcnss-wlan";
1494 interrupt-names = "tx", "rx";
1496 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1497 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1504 compatible = "arm,coresight-etb10", "arm,primecell";
1508 clock-names = "apb_pclk";
1510 in-ports {
1513 remote-endpoint = <&replicator_out0>;
1520 compatible = "arm,coresight-tpiu", "arm,primecell";
1524 clock-names = "apb_pclk";
1526 in-ports {
1529 remote-endpoint = <&replicator_out1>;
1536 compatible = "arm,coresight-static-replicator";
1539 clock-names = "apb_pclk";
1541 out-ports {
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1548 remote-endpoint = <&etb_in>;
1554 remote-endpoint = <&tpiu_in>;
1559 in-ports {
1562 remote-endpoint = <&funnel_out>;
1569 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1573 clock-names = "apb_pclk";
1575 in-ports {
1576 #address-cells = <1>;
1577 #size-cells = <0>;
1581 * 2 - connected to STM component
1582 * 3 - not-connected
1583 * 6 - not-connected
1584 * 7 - not-connected
1589 remote-endpoint = <&etm0_out>;
1595 remote-endpoint = <&etm1_out>;
1601 remote-endpoint = <&etm2_out>;
1607 remote-endpoint = <&etm3_out>;
1612 out-ports {
1615 remote-endpoint = <&replicator_in>;
1622 compatible = "arm,coresight-etm3x", "arm,primecell";
1626 clock-names = "apb_pclk";
1630 out-ports {
1633 remote-endpoint = <&funnel_in0>;
1640 compatible = "arm,coresight-etm3x", "arm,primecell";
1644 clock-names = "apb_pclk";
1648 out-ports {
1651 remote-endpoint = <&funnel_in1>;
1658 compatible = "arm,coresight-etm3x", "arm,primecell";
1662 clock-names = "apb_pclk";
1666 out-ports {
1669 remote-endpoint = <&funnel_in4>;
1676 compatible = "arm,coresight-etm3x", "arm,primecell";
1680 clock-names = "apb_pclk";
1684 out-ports {
1687 remote-endpoint = <&funnel_in5>;
1694 #include "qcom-apq8064-pins.dtsi"