Lines Matching +full:0 +full:x07500000
25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x0>;
111 coefficients = <1199 0>;
132 coefficients = <1132 0>;
153 coefficients = <1199 0>;
174 coefficients = <1132 0>;
199 #clock-cells = <0>;
205 #clock-cells = <0>;
211 #clock-cells = <0>;
218 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
233 #size-cells = <0>;
238 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
240 apps_smsm: apps@0 {
241 reg = <0>;
295 reg = <0x800000 0x4000>;
298 gpio-ranges = <&tlmm_pinmux 0 0 90>;
305 pinctrl-0 = <&ps_hold_default_state>;
310 reg = <0x01200000 0x8000>;
317 reg = <0x02000000 0x1000>,
318 <0x02002000 0x1000>;
327 reg = <0x0200a000 0x100>;
329 cpu-offset = <0x80000>;
334 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
338 #clock-cells = <0>;
343 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
347 #clock-cells = <0>;
352 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
356 #clock-cells = <0>;
361 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
365 #clock-cells = <0>;
370 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
380 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
390 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
400 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
410 reg = <0x12100000 0x10000>;
417 reg = <0x12440000 0x100>;
428 reg = <0x12450000 0x100>,
429 <0x12400000 0x03>;
438 pinctrl-0 = <&i2c1_default_state>;
441 reg = <0x12460000 0x1000>;
446 #size-cells = <0>;
456 reg = <0x12480000 0x100>;
467 reg = <0x124a0000 0x1000>;
468 pinctrl-0 = <&i2c2_default_state>;
475 #size-cells = <0>;
484 reg = <0x16200000 0x100>;
492 pinctrl-0 = <&i2c3_default_state>;
495 reg = <0x16280000 0x1000>;
501 #size-cells = <0>;
510 reg = <0x16300000 0x03>;
519 reg = <0x16340000 0x100>,
520 <0x16300000 0x3>;
522 pinctrl-0 = <&gsbi4_uart_pin_a>;
531 pinctrl-0 = <&i2c4_default_state>;
534 reg = <0x16380000 0x1000>;
547 reg = <0x1a200000 0x03>;
556 reg = <0x1a240000 0x100>,
557 <0x1a200000 0x03>;
566 reg = <0x1a280000 0x1000>;
568 pinctrl-0 = <&spi5_default_state>;
575 #size-cells = <0>;
583 reg = <0x16500000 0x03>;
592 reg = <0x16540000 0x100>,
593 <0x16500000 0x03>;
602 pinctrl-0 = <&i2c6_default_state>;
605 reg = <0x16580000 0x1000>;
618 reg = <0x16600000 0x100>;
628 reg = <0x16640000 0x1000>,
629 <0x16600000 0x1000>;
638 pinctrl-0 = <&i2c7_default_state>;
641 reg = <0x16680000 0x1000>;
652 reg = <0x1a500000 0x200>;
659 reg = <0x00c00000 0x1000>;
665 reg = <0x00500000 0x1000>;
671 reg = <0x00700000 0x1000>;
676 reg = <0x404 0x10>;
679 reg = <0x414 0x10>;
685 reg = <0x00900000 0x4000>;
708 reg = <0x28000000 0x1000>;
713 <0>,
714 <0>, <0>,
715 <0>, <0>,
716 <0>;
729 reg = <0x4000000 0x1000>;
737 <&dsi0_phy 0>,
739 <&dsi1_phy 0>,
753 reg = <0x2011000 0x1000>;
756 #clock-cells = <0>;
761 reg = <0x108000 0x1000>;
762 qcom,ipc = <&l2cc 0x8 2>;
779 reg = <0x12500000 0x200>,
780 <0x12500200 0x200>;
789 ahb-burst-config = <0>;
801 resets = <&usb1 0>;
803 #phy-cells = <0>;
810 reg = <0x12520000 0x200>,
811 <0x12520200 0x200>;
820 ahb-burst-config = <0>;
830 #phy-cells = <0>;
833 resets = <&usb3 0>;
841 reg = <0x12530000 0x200>,
842 <0x12530200 0x200>;
851 ahb-burst-config = <0>;
861 #phy-cells = <0>;
864 resets = <&usb4 0>;
873 reg = <0x1b400000 0x200>;
876 #phy-cells = <0>;
882 reg = <0x29000000 0x180>;
902 ports-implemented = <0x1>;
907 arm,primecell-periphid = <0x00051180>;
909 reg = <0x12180000 0x2000>;
924 reg = <0x12182000 0x8000>;
929 qcom,ee = <0>;
934 arm,primecell-periphid = <0x00051180>;
936 reg = <0x121c0000 0x2000>;
947 pinctrl-0 = <&sdc4_default_state>;
952 reg = <0x121c2000 0x8000>;
957 qcom,ee = <0>;
964 pinctrl-0 = <&sdcc1_default_state>;
965 arm,primecell-periphid = <0x00051180>;
966 reg = <0x12400000 0x2000>;
981 reg = <0x12402000 0x8000>;
986 qcom,ee = <0>;
991 reg = <0x1a400000 0x100>;
996 reg = <0x04300000 0x20000>;
1011 iommus = <&gfx3d 0
1043 &gfx3d1 0
1093 reg = <0x5700000 0x70>;
1100 #size-cells = <0>;
1102 reg = <0x04700000 0x200>;
1120 assigned-clock-parents = <&dsi0_phy 0>,
1121 <&dsi0_phy 0>,
1130 #size-cells = <0>;
1132 port@0 {
1133 reg = <0>;
1150 #phy-cells = <0>;
1152 reg = <0x04700200 0x100>,
1153 <0x04700300 0x200>,
1154 <0x04700500 0x5c>;
1165 reg = <0x05800000 0x200>;
1187 assigned-clock-parents = <&dsi1_phy 0>,
1188 <&dsi1_phy 0>,
1196 #size-cells = <0>;
1202 #size-cells = <0>;
1204 port@0 {
1205 reg = <0>;
1221 reg = <0x05800200 0x100>,
1222 <0x05800300 0x200>,
1223 <0x05800500 0x5c>;
1232 #phy-cells = <0>;
1246 reg = <0x07500000 0x100000>;
1262 reg = <0x07600000 0x100000>;
1278 reg = <0x07c00000 0x100000>;
1294 reg = <0x07d00000 0x100000>;
1303 reg = <0x1b500000 0x1000>,
1304 <0x1b502000 0x80>,
1305 <0x1b600000 0x100>,
1306 <0x0ff00000 0x100000>;
1309 linux,pci-domain = <0>;
1310 bus-range = <0x00 0xff>;
1314 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
1315 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
1319 interrupt-map-mask = <0 0 0 0x7>;
1320 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1321 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1322 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1323 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1336 pcie@0 {
1338 reg = <0x0 0x0 0x0 0x0 0x0>;
1339 bus-range = <0x01 0xff>;
1350 pinctrl-0 = <&hdmi_pinctrl>;
1351 reg = <0x04a00000 0x2f0>;
1367 #size-cells = <0>;
1369 port@0 {
1370 reg = <0>;
1385 reg = <0x4a00400 0x60>,
1386 <0x4a00500 0x100>;
1392 #phy-cells = <0>;
1393 #clock-cells = <0>;
1400 reg = <0x05100000 0xf0000>;
1415 iommus = <&mdp_port0 0
1417 &mdp_port1 0
1422 #size-cells = <0>;
1424 port@0 {
1425 reg = <0>;
1453 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1505 reg = <0x1a01000 0x1000>;
1521 reg = <0x1a03000 0x1000>;
1543 #size-cells = <0>;
1545 port@0 {
1546 reg = <0>;
1570 reg = <0x1a04000 0x1000>;
1577 #size-cells = <0>;
1586 port@0 {
1587 reg = <0>;
1623 reg = <0x1a1c000 0x1000>;
1641 reg = <0x1a1d000 0x1000>;
1659 reg = <0x1a1e000 0x1000>;
1677 reg = <0x1a1f000 0x1000>;