Lines Matching refs:clks
76 clocks = <&clks IMX7D_CLK_ARM>;
113 clocks = <&clks IMX7D_USB_PHY1_CLK>;
120 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
219 clocks = <&clks IMX7D_OCRAM_CLK>;
225 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
256 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
271 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
306 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
329 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
344 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
463 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
470 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
478 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
486 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
500 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
501 <&clks IMX7D_GPT1_ROOT_CLK>;
509 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
510 <&clks IMX7D_GPT2_ROOT_CLK>;
519 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
520 <&clks IMX7D_GPT3_ROOT_CLK>;
529 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
530 <&clks IMX7D_GPT4_ROOT_CLK>;
539 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
566 clocks = <&clks IMX7D_OCOTP_CLK>;
619 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
634 clocks = <&clks IMX7D_SNVS_CLK>;
651 clocks = <&clks IMX7D_SNVS_CLK>;
659 clks: clock-controller@30380000 { label
720 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
730 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
742 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
743 <&clks IMX7D_ECSPI4_ROOT_CLK>;
757 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
758 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
759 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
760 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>;
771 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
772 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
773 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
774 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>;
782 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
783 <&clks IMX7D_PWM1_ROOT_CLK>;
793 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
794 <&clks IMX7D_PWM2_ROOT_CLK>;
804 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
805 <&clks IMX7D_PWM3_ROOT_CLK>;
815 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
816 <&clks IMX7D_PWM4_ROOT_CLK>;
826 clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>;
841 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
842 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
851 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
852 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
853 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
883 clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>,
884 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
886 assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>,
887 <&clks IMX7D_PLL_SYS_PFD5_CLK>;
888 assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>;
919 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
920 <&clks IMX7D_ECSPI1_ROOT_CLK>;
933 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
934 <&clks IMX7D_ECSPI2_ROOT_CLK>;
947 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
948 <&clks IMX7D_ECSPI3_ROOT_CLK>;
960 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
961 <&clks IMX7D_UART1_ROOT_CLK>;
971 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
972 <&clks IMX7D_UART2_ROOT_CLK>;
982 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
983 <&clks IMX7D_UART3_ROOT_CLK>;
993 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
994 <&clks IMX7D_SAI1_ROOT_CLK>,
995 <&clks IMX7D_CLK_DUMMY>,
996 <&clks IMX7D_CLK_DUMMY>;
1008 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
1009 <&clks IMX7D_SAI2_ROOT_CLK>,
1010 <&clks IMX7D_CLK_DUMMY>,
1011 <&clks IMX7D_CLK_DUMMY>;
1023 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
1024 <&clks IMX7D_SAI3_ROOT_CLK>,
1025 <&clks IMX7D_CLK_DUMMY>,
1026 <&clks IMX7D_CLK_DUMMY>;
1041 clocks = <&clks IMX7D_CAAM_CLK>,
1042 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1068 clocks = <&clks IMX7D_CLK_DUMMY>,
1069 <&clks IMX7D_CAN1_ROOT_CLK>;
1079 clocks = <&clks IMX7D_CLK_DUMMY>,
1080 <&clks IMX7D_CAN2_ROOT_CLK>;
1092 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
1102 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1112 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1122 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1131 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1132 <&clks IMX7D_UART4_ROOT_CLK>;
1142 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1143 <&clks IMX7D_UART5_ROOT_CLK>;
1153 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1154 <&clks IMX7D_UART6_ROOT_CLK>;
1164 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1165 <&clks IMX7D_UART7_ROOT_CLK>;
1174 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1183 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1193 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1204 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1229 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1230 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1231 <&clks IMX7D_USDHC1_ROOT_CLK>;
1243 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1244 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1245 <&clks IMX7D_USDHC2_ROOT_CLK>;
1257 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1258 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1259 <&clks IMX7D_USDHC3_ROOT_CLK>;
1274 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
1275 <&clks IMX7D_QSPI_ROOT_CLK>;
1284 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1285 <&clks IMX7D_SDMA_CORE_CLK>;
1299 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1300 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1301 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1302 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1303 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1322 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1333 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1334 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1339 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1340 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;