Lines Matching +full:imx7d +full:- +full:ccm
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
19 * pre-existing /chosen node to be available to insert the
55 #address-cells = <1>;
56 #size-cells = <0>;
58 idle-states {
59 entry-method = "psci";
61 cpu_sleep_wait: cpu-sleep-wait {
62 compatible = "arm,idle-state";
63 arm,psci-suspend-param = <0x0010000>;
64 local-timer-stop;
65 entry-latency-us = <100>;
66 exit-latency-us = <50>;
67 min-residency-us = <1000>;
72 compatible = "arm,cortex-a7";
75 clock-frequency = <792000000>;
77 cpu-idle-states = <&cpu_sleep_wait>;
78 operating-points-v2 = <&cpu0_opp_table>;
79 #cooling-cells = <2>;
80 nvmem-cells = <&fuse_grade>;
81 nvmem-cell-names = "speed_grade";
85 cpu0_opp_table: opp-table {
86 compatible = "operating-points-v2";
87 opp-shared;
89 opp-792000000 {
90 opp-hz = /bits/ 64 <792000000>;
91 opp-microvolt = <1000000>;
92 clock-latency-ns = <150000>;
93 opp-supported-hw = <0xf>, <0xf>;
97 ckil: clock-cki {
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
100 clock-frequency = <32768>;
101 clock-output-names = "ckil";
104 osc: clock-osc {
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
107 clock-frequency = <24000000>;
108 clock-output-names = "osc";
112 compatible = "usb-nop-xceiv";
114 clock-names = "main_clk";
115 #phy-cells = <0>;
119 compatible = "usb-nop-xceiv";
121 clock-names = "main_clk";
122 power-domains = <&pgc_hsic_phy>;
123 #phy-cells = <0>;
127 compatible = "arm,cortex-a7-pmu";
128 interrupt-parent = <&gpc>;
130 interrupt-affinity = <&cpu0>;
135 * non-configurable replicators don't show up on the
138 compatible = "arm,coresight-static-replicator";
140 out-ports {
141 #address-cells = <1>;
142 #size-cells = <0>;
147 remote-endpoint = <&tpiu_in_port>;
154 remote-endpoint = <&etr_in_port>;
159 in-ports {
162 remote-endpoint = <&etf_out_port>;
169 compatible = "arm,armv7-timer";
170 arm,cpu-registers-not-fw-configured;
171 interrupt-parent = <&intc>;
178 video_mux: csi-mux {
179 compatible = "video-mux";
180 mux-controls = <&mux 0>;
181 #address-cells = <1>;
182 #size-cells = <0>;
193 remote-endpoint = <&mipi_vc0_to_csi_mux>;
201 remote-endpoint = <&csi_from_csi_mux>;
207 #address-cells = <1>;
208 #size-cells = <1>;
209 compatible = "simple-bus";
210 interrupt-parent = <&gpc>;
214 compatible = "mmio-sram";
217 #address-cells = <1>;
218 #size-cells = <1>;
223 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
226 clock-names = "apb_pclk";
228 ca_funnel_in_ports: in-ports {
229 #address-cells = <1>;
230 #size-cells = <0>;
235 remote-endpoint = <&etm0_out_port>;
242 out-ports {
245 remote-endpoint = <&hugo_funnel_in_port0>;
253 compatible = "arm,coresight-etm3x", "arm,primecell";
257 clock-names = "apb_pclk";
259 out-ports {
262 remote-endpoint = <&ca_funnel_in_port0>;
269 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
272 clock-names = "apb_pclk";
274 in-ports {
275 #address-cells = <1>;
276 #size-cells = <0>;
281 remote-endpoint = <&ca_funnel_out_port0>;
294 out-ports {
297 remote-endpoint = <&etf_in_port>;
304 compatible = "arm,coresight-tmc", "arm,primecell";
307 clock-names = "apb_pclk";
309 in-ports {
312 remote-endpoint = <&hugo_funnel_out_port0>;
317 out-ports {
320 remote-endpoint = <&replicator_in_port0>;
327 compatible = "arm,coresight-tmc", "arm,primecell";
330 clock-names = "apb_pclk";
332 in-ports {
335 remote-endpoint = <&replicator_out_port1>;
342 compatible = "arm,coresight-tpiu", "arm,primecell";
345 clock-names = "apb_pclk";
347 in-ports {
350 remote-endpoint = <&replicator_out_port0>;
356 intc: interrupt-controller@31001000 {
357 compatible = "arm,cortex-a7-gic";
359 #interrupt-cells = <3>;
360 interrupt-controller;
361 interrupt-parent = <&intc>;
369 compatible = "fsl,aips-bus", "simple-bus";
370 #address-cells = <1>;
371 #size-cells = <1>;
376 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
388 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
392 gpio-controller;
393 #gpio-cells = <2>;
394 interrupt-controller;
395 #interrupt-cells = <2>;
396 gpio-ranges = <&iomuxc 0 13 32>;
400 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
404 gpio-controller;
405 #gpio-cells = <2>;
406 interrupt-controller;
407 #interrupt-cells = <2>;
408 gpio-ranges = <&iomuxc 0 45 29>;
412 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
416 gpio-controller;
417 #gpio-cells = <2>;
418 interrupt-controller;
419 #interrupt-cells = <2>;
420 gpio-ranges = <&iomuxc 0 74 24>;
424 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
428 gpio-controller;
429 #gpio-cells = <2>;
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 gpio-ranges = <&iomuxc 0 98 18>;
436 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
440 gpio-controller;
441 #gpio-cells = <2>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 gpio-ranges = <&iomuxc 0 116 23>;
448 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
452 gpio-controller;
453 #gpio-cells = <2>;
454 interrupt-controller;
455 #interrupt-cells = <2>;
456 gpio-ranges = <&iomuxc 0 139 16>;
460 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
467 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
475 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
483 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
491 compatible = "fsl,imx7d-iomuxc-lpsr";
493 fsl,input-sel = <&iomuxc>;
497 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
502 clock-names = "ipg", "per";
506 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
511 clock-names = "ipg", "per";
516 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
521 clock-names = "ipg", "per";
526 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
531 clock-names = "ipg", "per";
536 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
544 compatible = "fsl,imx7d-iomuxc";
548 gpr: iomuxc-gpr@30340000 {
549 compatible = "fsl,imx7d-iomuxc-gpr",
550 "fsl,imx6q-iomuxc-gpr", "syscon",
551 "simple-mfd";
554 mux: mux-controller {
555 compatible = "mmio-mux";
556 #mux-control-cells = <1>;
557 mux-reg-masks = <0x14 0x00000010>;
562 #address-cells = <1>;
563 #size-cells = <1>;
564 compatible = "fsl,imx7d-ocotp", "syscon";
572 fuse_grade: fuse-grade@10 {
578 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
579 "syscon", "simple-mfd";
584 reg_1p0d: regulator-vdd1p0d {
585 compatible = "fsl,anatop-regulator";
586 regulator-name = "vdd1p0d";
587 regulator-min-microvolt = <800000>;
588 regulator-max-microvolt = <1200000>;
589 anatop-reg-offset = <0x210>;
590 anatop-vol-bit-shift = <8>;
591 anatop-vol-bit-width = <5>;
592 anatop-min-bit-val = <8>;
593 anatop-min-voltage = <800000>;
594 anatop-max-voltage = <1200000>;
595 anatop-enable-bit = <0>;
598 reg_1p2: regulator-vdd1p2 {
599 compatible = "fsl,anatop-regulator";
600 regulator-name = "vdd1p2";
601 regulator-min-microvolt = <1100000>;
602 regulator-max-microvolt = <1300000>;
603 anatop-reg-offset = <0x220>;
604 anatop-vol-bit-shift = <8>;
605 anatop-vol-bit-width = <5>;
606 anatop-min-bit-val = <0x14>;
607 anatop-min-voltage = <1100000>;
608 anatop-max-voltage = <1300000>;
609 anatop-enable-bit = <0>;
613 compatible = "fsl,imx7d-tempmon";
614 interrupt-parent = <&gpc>;
617 nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
618 nvmem-cell-names = "calib", "temp_grade";
620 #thermal-sensor-cells = <0>;
625 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
628 snvs_rtc: snvs-rtc-lp {
629 compatible = "fsl,sec-v4.0-mon-rtc-lp";
635 clock-names = "snvs-rtc";
638 snvs_poweroff: snvs-poweroff {
639 compatible = "syscon-poweroff";
647 snvs_pwrkey: snvs-powerkey {
648 compatible = "fsl,sec-v4.0-pwrkey";
652 clock-names = "snvs-pwrkey";
654 wakeup-source;
659 clks: clock-controller@30380000 {
660 compatible = "fsl,imx7d-ccm";
664 #clock-cells = <1>;
666 clock-names = "ckil", "osc";
669 src: reset-controller@30390000 {
670 compatible = "fsl,imx7d-src", "syscon";
673 #reset-cells = <1>;
677 compatible = "fsl,imx7d-gpc";
679 interrupt-controller;
681 #interrupt-cells = <3>;
682 interrupt-parent = <&intc>;
685 #address-cells = <1>;
686 #size-cells = <0>;
688 pgc_mipi_phy: power-domain@0 {
689 #power-domain-cells = <0>;
691 power-supply = <®_1p0d>;
694 pgc_pcie_phy: power-domain@1 {
695 #power-domain-cells = <0>;
697 power-supply = <®_1p0d>;
700 pgc_hsic_phy: power-domain@2 {
701 #power-domain-cells = <0>;
703 power-supply = <®_1p2>;
710 compatible = "fsl,aips-bus", "simple-bus";
711 #address-cells = <1>;
712 #size-cells = <1>;
717 compatible = "fsl,imx7d-adc";
721 clock-names = "adc";
722 #io-channel-cells = <1>;
727 compatible = "fsl,imx7d-adc";
731 clock-names = "adc";
732 #io-channel-cells = <1>;
737 #address-cells = <1>;
738 #size-cells = <0>;
739 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
744 clock-names = "ipg", "per";
745 dma-names = "rx", "tx";
751 compatible = "fsl,vf610-ftm-pwm";
753 #pwm-cells = <3>;
755 clock-names = "ftm_sys", "ftm_ext",
765 compatible = "fsl,vf610-ftm-pwm";
767 #pwm-cells = <3>;
769 clock-names = "ftm_sys", "ftm_ext",
779 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
784 clock-names = "ipg", "per";
785 #pwm-cells = <3>;
790 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
795 clock-names = "ipg", "per";
796 #pwm-cells = <3>;
801 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
806 clock-names = "ipg", "per";
807 #pwm-cells = <3>;
812 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
817 clock-names = "ipg", "per";
818 #pwm-cells = <3>;
823 compatible = "fsl,imx7-csi";
827 clock-names = "mclk";
832 remote-endpoint = <&csi_mux_to_csi>;
838 compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif";
843 clock-names = "pix", "axi";
847 mipi_csi: mipi-csi@30750000 {
848 compatible = "fsl,imx7-mipi-csi2";
854 clock-names = "pclk", "wrap", "phy";
855 power-domains = <&pgc_mipi_phy>;
856 phy-supply = <®_1p0d>;
861 #address-cells = <1>;
862 #size-cells = <0>;
872 remote-endpoint = <&csi_mux_from_mipi_vc0>;
879 compatible = "fsl,imx7d-mipi-dsim", "fsl,imx8mm-mipi-dsim";
880 #address-cells = <1>;
881 #size-cells = <0>;
885 clock-names = "bus_clk", "sclk_mipi";
886 assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>,
888 assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>;
889 assigned-clock-rates = <0>, <333000000>;
890 power-domains = <&pgc_mipi_phy>;
892 samsung,burst-clock-frequency = <891000000>;
893 samsung,esc-clock-frequency = <20000000>;
894 samsung,pll-clock-frequency = <24000000>;
900 compatible = "fsl,aips-bus", "simple-bus";
901 #address-cells = <1>;
902 #size-cells = <1>;
906 spba-bus@30800000 {
907 compatible = "fsl,spba-bus", "simple-bus";
908 #address-cells = <1>;
909 #size-cells = <1>;
914 #address-cells = <1>;
915 #size-cells = <0>;
916 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
921 clock-names = "ipg", "per";
922 dma-names = "rx", "tx";
928 #address-cells = <1>;
929 #size-cells = <0>;
930 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
935 clock-names = "ipg", "per";
936 dma-names = "rx", "tx";
942 #address-cells = <1>;
943 #size-cells = <0>;
944 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
949 clock-names = "ipg", "per";
950 dma-names = "rx", "tx";
956 compatible = "fsl,imx7d-uart",
957 "fsl,imx6q-uart";
962 clock-names = "ipg", "per";
967 compatible = "fsl,imx7d-uart",
968 "fsl,imx6q-uart";
973 clock-names = "ipg", "per";
978 compatible = "fsl,imx7d-uart",
979 "fsl,imx6q-uart";
984 clock-names = "ipg", "per";
989 #sound-dai-cells = <0>;
990 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
997 clock-names = "bus", "mclk1", "mclk2", "mclk3";
998 dma-names = "rx", "tx";
1004 #sound-dai-cells = <0>;
1005 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
1012 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1013 dma-names = "rx", "tx";
1019 #sound-dai-cells = <0>;
1020 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
1027 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1028 dma-names = "rx", "tx";
1035 compatible = "fsl,sec-v4.0";
1036 #address-cells = <1>;
1037 #size-cells = <1>;
1043 clock-names = "ipg", "aclk";
1046 compatible = "fsl,sec-v4.0-job-ring";
1052 compatible = "fsl,sec-v4.0-job-ring";
1058 compatible = "fsl,sec-v4.0-job-ring";
1065 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1070 clock-names = "ipg", "per";
1071 fsl,stop-mode = <&gpr 0x10 1>;
1076 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1081 clock-names = "ipg", "per";
1082 fsl,stop-mode = <&gpr 0x10 2>;
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1089 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1097 #address-cells = <1>;
1098 #size-cells = <0>;
1099 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1109 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1119 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1127 compatible = "fsl,imx7d-uart",
1128 "fsl,imx6q-uart";
1133 clock-names = "ipg", "per";
1138 compatible = "fsl,imx7d-uart",
1139 "fsl,imx6q-uart";
1144 clock-names = "ipg", "per";
1149 compatible = "fsl,imx7d-uart",
1150 "fsl,imx6q-uart";
1155 clock-names = "ipg", "per";
1160 compatible = "fsl,imx7d-uart",
1161 "fsl,imx6q-uart";
1166 clock-names = "ipg", "per";
1171 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1175 #mbox-cells = <2>;
1180 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1184 #mbox-cells = <2>;
1185 fsl,mu-side-b;
1190 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1196 phy-clkgate-delay-us = <400>;
1201 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1209 phy-clkgate-delay-us = <400>;
1214 #index-cells = <1>;
1215 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1220 #index-cells = <1>;
1221 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1226 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1232 clock-names = "ipg", "ahb", "per";
1233 bus-width = <4>;
1234 fsl,tuning-step = <2>;
1235 fsl,tuning-start-tap = <20>;
1240 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1246 clock-names = "ipg", "ahb", "per";
1247 bus-width = <4>;
1248 fsl,tuning-step = <2>;
1249 fsl,tuning-start-tap = <20>;
1254 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1260 clock-names = "ipg", "ahb", "per";
1261 bus-width = <4>;
1262 fsl,tuning-step = <2>;
1263 fsl,tuning-start-tap = <20>;
1268 compatible = "fsl,imx7d-qspi";
1270 reg-names = "QuadSPI", "QuadSPI-memory";
1271 #address-cells = <1>;
1272 #size-cells = <0>;
1276 clock-names = "qspi_en", "qspi";
1280 sdma: dma-controller@30bd0000 {
1281 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1286 clock-names = "ipg", "ahb";
1287 #dma-cells = <3>;
1288 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1292 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1294 interrupt-names = "int0", "int1", "int2", "pps";
1304 clock-names = "ipg", "ahb", "ptp",
1306 fsl,num-tx-queues = <3>;
1307 fsl,num-rx-queues = <3>;
1308 fsl,stop-mode = <&gpr 0x10 3>;
1313 dma_apbh: dma-controller@33000000 {
1314 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1320 #dma-cells = <1>;
1321 dma-channels = <4>;
1325 gpmi: nand-controller@33002000 {
1326 compatible = "fsl,imx7d-gpmi-nand";
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1330 reg-names = "gpmi-nand", "bch";
1332 interrupt-names = "bch";
1335 clock-names = "gpmi_io", "gpmi_bch_apb";
1337 dma-names = "rx-tx";
1339 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1340 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;