Lines Matching full:clks
77 clocks = <&clks IMX7D_CLK_ARM>;
114 clocks = <&clks IMX7D_USB_PHY1_CLK>;
121 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
192 clocks = <&clks IMX7D_OCRAM_CLK>;
198 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
229 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
244 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
279 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
302 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
317 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
436 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
443 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
451 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
459 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
473 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
474 <&clks IMX7D_GPT1_ROOT_CLK>;
482 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
483 <&clks IMX7D_GPT2_ROOT_CLK>;
492 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
493 <&clks IMX7D_GPT3_ROOT_CLK>;
502 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
503 <&clks IMX7D_GPT4_ROOT_CLK>;
512 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
567 clocks = <&clks IMX7D_OCOTP_CLK>;
620 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
635 clocks = <&clks IMX7D_SNVS_CLK>;
652 clocks = <&clks IMX7D_SNVS_CLK>;
660 clks: clock-controller@30380000 { label
721 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
731 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
743 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
744 <&clks IMX7D_ECSPI4_ROOT_CLK>;
758 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
759 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
760 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
761 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>;
772 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
773 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
774 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
775 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>;
783 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
784 <&clks IMX7D_PWM1_ROOT_CLK>;
794 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
795 <&clks IMX7D_PWM2_ROOT_CLK>;
805 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
806 <&clks IMX7D_PWM3_ROOT_CLK>;
816 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
817 <&clks IMX7D_PWM4_ROOT_CLK>;
827 clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>;
842 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
843 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
852 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
853 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
854 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
884 clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>,
885 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
887 assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>,
888 <&clks IMX7D_PLL_SYS_PFD5_CLK>;
889 assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>;
920 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
921 <&clks IMX7D_ECSPI1_ROOT_CLK>;
934 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
935 <&clks IMX7D_ECSPI2_ROOT_CLK>;
948 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
949 <&clks IMX7D_ECSPI3_ROOT_CLK>;
961 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
962 <&clks IMX7D_UART1_ROOT_CLK>;
972 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
973 <&clks IMX7D_UART2_ROOT_CLK>;
983 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
984 <&clks IMX7D_UART3_ROOT_CLK>;
994 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
995 <&clks IMX7D_SAI1_ROOT_CLK>,
996 <&clks IMX7D_CLK_DUMMY>,
997 <&clks IMX7D_CLK_DUMMY>;
1009 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
1010 <&clks IMX7D_SAI2_ROOT_CLK>,
1011 <&clks IMX7D_CLK_DUMMY>,
1012 <&clks IMX7D_CLK_DUMMY>;
1024 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
1025 <&clks IMX7D_SAI3_ROOT_CLK>,
1026 <&clks IMX7D_CLK_DUMMY>,
1027 <&clks IMX7D_CLK_DUMMY>;
1042 clocks = <&clks IMX7D_CAAM_CLK>,
1043 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1069 clocks = <&clks IMX7D_CLK_DUMMY>,
1070 <&clks IMX7D_CAN1_ROOT_CLK>;
1080 clocks = <&clks IMX7D_CLK_DUMMY>,
1081 <&clks IMX7D_CAN2_ROOT_CLK>;
1093 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
1103 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1113 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1123 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1132 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1133 <&clks IMX7D_UART4_ROOT_CLK>;
1143 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1144 <&clks IMX7D_UART5_ROOT_CLK>;
1154 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1155 <&clks IMX7D_UART6_ROOT_CLK>;
1165 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1166 <&clks IMX7D_UART7_ROOT_CLK>;
1175 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1184 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1194 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1205 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1230 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1231 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1232 <&clks IMX7D_USDHC1_ROOT_CLK>;
1244 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1245 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1246 <&clks IMX7D_USDHC2_ROOT_CLK>;
1258 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1259 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1260 <&clks IMX7D_USDHC3_ROOT_CLK>;
1275 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
1276 <&clks IMX7D_QSPI_ROOT_CLK>;
1285 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1286 <&clks IMX7D_SDMA_CORE_CLK>;
1300 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1301 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1302 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1303 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1304 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1323 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1334 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1335 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1340 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1341 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;