Lines Matching +full:0 +full:x30340000
56 #size-cells = <0>;
63 arm,psci-suspend-param = <0x0010000>;
71 cpu0: cpu@0 {
74 reg = <0>;
94 opp-supported-hw = <0xf>, <0xf>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
116 #phy-cells = <0>;
124 #phy-cells = <0>;
143 #size-cells = <0>;
145 port@0 {
146 reg = <0>;
188 reg = <0x00900000 0x20000>;
189 ranges = <0 0x00900000 0x20000>;
197 reg = <0x30041000 0x1000>;
203 #size-cells = <0>;
205 port@0 {
206 reg = <0>;
227 reg = <0x3007c000 0x1000>;
243 reg = <0x30083000 0x1000>;
249 #size-cells = <0>;
251 port@0 {
252 reg = <0>;
278 reg = <0x30084000 0x1000>;
301 reg = <0x30086000 0x1000>;
316 reg = <0x30087000 0x1000>;
335 reg = <0x31001000 0x1000>,
336 <0x31002000 0x2000>,
337 <0x31004000 0x2000>,
338 <0x31006000 0x2000>;
345 reg = <0x30000000 0x400000>;
350 reg = <0x30200000 0x10000>;
357 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
362 reg = <0x30210000 0x10000>;
369 gpio-ranges = <&iomuxc 0 13 32>;
374 reg = <0x30220000 0x10000>;
381 gpio-ranges = <&iomuxc 0 45 29>;
386 reg = <0x30230000 0x10000>;
393 gpio-ranges = <&iomuxc 0 74 24>;
398 reg = <0x30240000 0x10000>;
405 gpio-ranges = <&iomuxc 0 98 18>;
410 reg = <0x30250000 0x10000>;
417 gpio-ranges = <&iomuxc 0 116 23>;
422 reg = <0x30260000 0x10000>;
429 gpio-ranges = <&iomuxc 0 139 16>;
434 reg = <0x30280000 0x10000>;
441 reg = <0x30290000 0x10000>;
449 reg = <0x302a0000 0x10000>;
457 reg = <0x302b0000 0x10000>;
465 reg = <0x302c0000 0x10000>;
471 reg = <0x302d0000 0x10000>;
480 reg = <0x302e0000 0x10000>;
490 reg = <0x302f0000 0x10000>;
500 reg = <0x30300000 0x10000>;
510 reg = <0x30320000 0x10000>;
518 reg = <0x30330000 0x10000>;
525 reg = <0x30340000 0x10000>;
530 mux-reg-masks = <0x14 0x00000010>;
535 mux-controls = <&mux 0>;
537 #size-cells = <0>;
540 port@0 {
541 reg = <0>;
566 reg = <0x30350000 0x10000>;
570 reg = <0x3c 0x4>;
574 reg = <0x10 0x4>;
581 reg = <0x30360000 0x10000>;
590 anatop-reg-offset = <0x210>;
596 anatop-enable-bit = <0>;
604 anatop-reg-offset = <0x220>;
607 anatop-min-bit-val = <0x14>;
610 anatop-enable-bit = <0>;
621 #thermal-sensor-cells = <0>;
626 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
627 reg = <0x30370000 0x10000>;
630 compatible = "fsl,sec-v4.0-mon-rtc-lp";
632 offset = <0x34>;
642 offset = <0x38>;
643 value = <0x60>;
644 mask = <0x60>;
649 compatible = "fsl,sec-v4.0-pwrkey";
662 reg = <0x30380000 0x10000>;
672 reg = <0x30390000 0x10000>;
679 reg = <0x303a0000 0x10000>;
687 #size-cells = <0>;
689 pgc_mipi_phy: power-domain@0 {
690 #power-domain-cells = <0>;
691 reg = <0>;
696 #power-domain-cells = <0>;
702 #power-domain-cells = <0>;
714 reg = <0x30400000 0x400000>;
719 reg = <0x30610000 0x10000>;
729 reg = <0x30620000 0x10000>;
739 #size-cells = <0>;
741 reg = <0x30630000 0x10000>;
753 reg = <0x30640000 0x10000>;
767 reg = <0x30650000 0x10000>;
781 reg = <0x30660000 0x10000>;
792 reg = <0x30670000 0x10000>;
803 reg = <0x30680000 0x10000>;
814 reg = <0x30690000 0x10000>;
825 reg = <0x30710000 0x10000>;
840 reg = <0x30730000 0x10000>;
850 reg = <0x30750000 0x10000>;
863 #size-cells = <0>;
865 port@0 {
866 reg = <0>;
882 #size-cells = <0>;
883 reg = <0x30760000 0x400>;
890 assigned-clock-rates = <0>, <333000000>;
904 reg = <0x30800000 0x400000>;
911 reg = <0x30800000 0x100000>;
916 #size-cells = <0>;
918 reg = <0x30820000 0x10000>;
924 dmas = <&sdma 0 7 1>, <&sdma 1 7 2>;
930 #size-cells = <0>;
932 reg = <0x30830000 0x10000>;
944 #size-cells = <0>;
946 reg = <0x30840000 0x10000>;
959 reg = <0x30860000 0x10000>;
970 reg = <0x30890000 0x10000>;
981 reg = <0x30880000 0x10000>;
990 #sound-dai-cells = <0>;
992 reg = <0x308a0000 0x10000>;
1000 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
1005 #sound-dai-cells = <0>;
1007 reg = <0x308b0000 0x10000>;
1015 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
1020 #sound-dai-cells = <0>;
1022 reg = <0x308c0000 0x10000>;
1030 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
1036 compatible = "fsl,sec-v4.0";
1039 reg = <0x30900000 0x40000>;
1040 ranges = <0 0x30900000 0x40000>;
1047 compatible = "fsl,sec-v4.0-job-ring";
1048 reg = <0x1000 0x1000>;
1053 compatible = "fsl,sec-v4.0-job-ring";
1054 reg = <0x2000 0x1000>;
1059 compatible = "fsl,sec-v4.0-job-ring";
1060 reg = <0x3000 0x1000>;
1067 reg = <0x30a00000 0x10000>;
1072 fsl,stop-mode = <&gpr 0x10 1>;
1078 reg = <0x30a10000 0x10000>;
1083 fsl,stop-mode = <&gpr 0x10 2>;
1089 #size-cells = <0>;
1091 reg = <0x30a20000 0x10000>;
1099 #size-cells = <0>;
1101 reg = <0x30a30000 0x10000>;
1109 #size-cells = <0>;
1111 reg = <0x30a40000 0x10000>;
1119 #size-cells = <0>;
1121 reg = <0x30a50000 0x10000>;
1130 reg = <0x30a60000 0x10000>;
1141 reg = <0x30a70000 0x10000>;
1152 reg = <0x30a80000 0x10000>;
1163 reg = <0x30a90000 0x10000>;
1173 reg = <0x30aa0000 0x10000>;
1182 reg = <0x30ab0000 0x10000>;
1192 reg = <0x30b10000 0x200>;
1196 fsl,usbmisc = <&usbmisc1 0>;
1203 reg = <0x30b30000 0x200>;
1207 fsl,usbmisc = <&usbmisc3 0>;
1217 reg = <0x30b10200 0x200>;
1223 reg = <0x30b30200 0x200>;
1228 reg = <0x30b40000 0x10000>;
1242 reg = <0x30b50000 0x10000>;
1256 reg = <0x30b60000 0x10000>;
1270 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
1273 #size-cells = <0>;
1283 reg = <0x30bd0000 0x10000>;
1294 reg = <0x30be0000 0x10000>;
1309 fsl,stop-mode = <&gpr 0x10 3>;
1316 reg = <0x33000000 0x2000>;
1329 #size-cells = <0>;
1330 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1337 dmas = <&dma_apbh 0>;