Lines Matching +full:0 +full:xb0
21 reg = <0x80000000 0x20000000>;
31 states = <1300000 0x1
32 1400000 0x0>;
37 #clock-cells = <0>;
54 pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>;
61 #size-cells = <0>;
68 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
78 pinctrl-0 = <&pinctrl_hog>;
82 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
83 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
84 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
85 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
86 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
87 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
88 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
89 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
95 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */
101 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
102 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
108 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */
109 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */
115 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
116 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
117 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
118 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
119 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
125 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
126 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
127 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
128 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
134 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
135 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
136 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
137 MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
143 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
144 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
145 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
146 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
147 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
148 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
149 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
150 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
151 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
152 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
158 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
159 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
160 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
161 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
162 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
163 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
164 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
165 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
166 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
167 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
173 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
174 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
175 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
176 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
177 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
178 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
179 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
180 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
181 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
182 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
193 pinctrl-0 = <&pinctrl_sai2>;
197 assigned-clock-rates = <0>, <12288000>;
208 pinctrl-0 = <&pinctrl_tsc>;
210 measure-delay-time = <0xffff>;
211 pre-charge-time = <0xfff>;
217 pinctrl-0 = <&pinctrl_uart2>;
224 pinctrl-0 = <&pinctrl_usdhc2>;