Lines Matching +full:0 +full:x10b0
15 reg = <0x80000000 0x80000000>;
21 pinctrl-0 = <&pinctrl_led>;
33 pinctrl-0 = <&pinctrl_vcc_sd3>;
102 #sound-dai-cells = <0>;
123 assigned-clock-rates = <0>, <0>, <24576000>;
128 pinctrl-0 = <&pinctrl_esai>;
132 assigned-clock-rates = <0>, <24576000>;
138 pinctrl-0 = <&pinctrl_enet1>;
146 #size-cells = <0>;
148 ethphy0: ethernet-phy@0 {
150 reg = <0>;
162 pinctrl-0 = <&pinctrl_enet2>;
171 pinctrl-0 = <&pinctrl_flexcan1>;
178 pinctrl-0 = <&pinctrl_flexcan2>;
185 pinctrl-0 = <&pinctrl_uart1>;
191 pinctrl-0 = <&pinctrl_usdhc3>;
205 pinctrl-0 = <&pinctrl_usdhc4>;
217 MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0
223 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
224 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
225 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
226 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
227 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
228 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
229 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
230 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
231 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
232 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
233 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
234 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
235 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
236 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
242 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
243 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
244 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
245 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
246 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
247 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
248 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
249 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
250 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
251 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
252 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
253 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
259 MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
260 MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
261 MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
262 MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
263 MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
264 MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
265 MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
266 MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
267 MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
268 MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
274 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
275 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
281 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
282 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
288 MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
289 MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
295 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
296 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
302 MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
308 MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
314 MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
315 MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
321 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
322 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
323 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
324 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
325 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
326 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
327 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
328 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
329 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
330 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
331 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
332 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
338 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
339 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
340 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
341 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
342 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
343 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
344 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
345 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
346 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
347 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
353 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
354 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
355 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
356 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
357 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
358 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
359 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
360 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
361 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
362 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
368 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
369 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
370 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
371 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
372 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
373 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
374 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
375 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
381 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
387 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
395 pinctrl-0 = <&pinctrl_i2c2>;
400 reg = <0x48>;
401 clocks = <&anaclk2 0>;
411 reg = <0x04>;
413 pinctrl-0 = <&pinctrl_egalax_int>;
421 reg = <0x08>;
523 reg = <0x68>;
532 pinctrl-0 = <&pinctrl_i2c3>;
537 reg = <0x30>;
544 reg = <0x32>;
552 pinctrl-0 = <&pinctrl_spdif>;
560 pinctrl-0 = <&pinctrl_wdog>;