Lines Matching +full:imx6ul +full:- +full:anatop
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright 2017-2018 NXP.
8 #include <dt-bindings/clock/imx6sll-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx6sll-pinfunc.h"
14 #address-cells = <1>;
15 #size-cells = <1>;
46 #address-cells = <1>;
47 #size-cells = <0>;
50 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
54 operating-points =
60 fsl,soc-operating-points =
61 /* ARM kHz SOC-PU uV */
66 clock-latency = <61036>; /* two CLK32 periods */
67 #cooling-cells = <2>;
73 clock-names = "arm", "pll2_pfd2_396m", "step",
75 nvmem-cells = <&cpu_speed_grade>;
76 nvmem-cell-names = "speed_grade";
80 ckil: clock-ckil {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <32768>;
84 clock-output-names = "ckil";
87 osc: clock-osc-24m {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <24000000>;
91 clock-output-names = "osc";
94 ipp_di0: clock-ipp-di0 {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <0>;
98 clock-output-names = "ipp_di0";
101 ipp_di1: clock-ipp-di1 {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <0>;
105 clock-output-names = "ipp_di1";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 compatible = "simple-bus";
112 interrupt-parent = <&gpc>;
116 compatible = "mmio-sram";
119 #address-cells = <1>;
120 #size-cells = <1>;
123 intc: interrupt-controller@a01000 {
124 compatible = "arm,cortex-a9-gic";
125 #interrupt-cells = <3>;
126 interrupt-controller;
129 interrupt-parent = <&intc>;
132 L2: cache-controller@a02000 {
133 compatible = "arm,pl310-cache";
136 cache-unified;
137 cache-level = <2>;
138 arm,tag-latency = <4 2 3>;
139 arm,data-latency = <4 2 3>;
143 compatible = "fsl,aips-bus", "simple-bus";
144 #address-cells = <1>;
145 #size-cells = <1>;
149 spba: spba-bus@2000000 {
150 compatible = "fsl,spba-bus", "simple-bus";
151 #address-cells = <1>;
152 #size-cells = <1>;
157 compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
161 dma-names = "rx", "tx";
172 clock-names = "core", "rxtx0",
181 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
185 dma-names = "rx", "tx";
188 clock-names = "ipg", "per";
193 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
197 dma-names = "rx", "tx";
200 clock-names = "ipg", "per";
205 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
209 dma-names = "rx", "tx";
212 clock-names = "ipg", "per";
217 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
221 dma-names = "rx", "tx";
224 clock-names = "ipg", "per";
229 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
230 "fsl,imx21-uart";
234 dma-names = "rx", "tx";
237 clock-names = "ipg", "per";
242 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
243 "fsl,imx21-uart";
247 dma-names = "rx", "tx";
250 clock-names = "ipg", "per";
255 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
256 "fsl,imx21-uart";
260 dma-names = "rx", "tx";
263 clock-names = "ipg", "per";
268 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
272 dma-names = "rx", "tx";
273 fsl,fifo-depth = <15>;
276 clock-names = "ipg", "baud";
281 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
285 dma-names = "rx", "tx";
286 fsl,fifo-depth = <15>;
289 clock-names = "ipg", "baud";
294 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
298 dma-names = "rx", "tx";
299 fsl,fifo-depth = <15>;
302 clock-names = "ipg", "baud";
307 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
308 "fsl,imx21-uart";
312 dma-name = "rx", "tx";
315 clock-names = "ipg", "per";
321 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
326 clock-names = "ipg", "per";
327 #pwm-cells = <3>;
331 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
336 clock-names = "ipg", "per";
337 #pwm-cells = <3>;
341 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
346 clock-names = "ipg", "per";
347 #pwm-cells = <3>;
351 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
356 clock-names = "ipg", "per";
357 #pwm-cells = <3>;
361 compatible = "fsl,imx6sl-gpt";
366 clock-names = "ipg", "per";
370 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
375 gpio-controller;
376 #gpio-cells = <2>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
379 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
383 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
388 gpio-controller;
389 #gpio-cells = <2>;
390 interrupt-controller;
391 #interrupt-cells = <2>;
392 gpio-ranges = <&iomuxc 0 50 32>;
396 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
401 gpio-controller;
402 #gpio-cells = <2>;
403 interrupt-controller;
404 #interrupt-cells = <2>;
405 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
411 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
416 gpio-controller;
417 #gpio-cells = <2>;
418 interrupt-controller;
419 #interrupt-cells = <2>;
420 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
432 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
437 gpio-controller;
438 #gpio-cells = <2>;
439 interrupt-controller;
440 #interrupt-cells = <2>;
441 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
455 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
460 gpio-controller;
461 #gpio-cells = <2>;
462 interrupt-controller;
463 #interrupt-cells = <2>;
467 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
475 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
482 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
489 clks: clock-controller@20c4000 {
490 compatible = "fsl,imx6sll-ccm";
494 #clock-cells = <1>;
496 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
498 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
499 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
502 anatop: anatop@20c8000 { label
503 compatible = "fsl,imx6sll-anatop",
504 "fsl,imx6q-anatop",
505 "syscon", "simple-mfd";
510 #address-cells = <1>;
511 #size-cells = <0>;
513 reg_3p0: regulator-3p0@20c8120 {
514 compatible = "fsl,anatop-regulator";
516 regulator-name = "vdd3p0";
517 regulator-min-microvolt = <2625000>;
518 regulator-max-microvolt = <3400000>;
519 anatop-reg-offset = <0x120>;
520 anatop-vol-bit-shift = <8>;
521 anatop-vol-bit-width = <5>;
522 anatop-min-bit-val = <0>;
523 anatop-min-voltage = <2625000>;
524 anatop-max-voltage = <3400000>;
525 anatop-enable-bit = <0>;
528 tempmon: temperature-sensor {
529 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
531 interrupt-parent = <&gpc>;
532 fsl,tempmon = <&anatop>;
533 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
534 nvmem-cell-names = "calib", "temp_grade";
539 usbphy1: usb-phy@20c9000 {
540 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
541 "fsl,imx23-usbphy";
545 phy-3p0-supply = <®_3p0>;
546 fsl,anatop = <&anatop>;
549 usbphy2: usb-phy@20ca000 {
550 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
551 "fsl,imx23-usbphy";
555 phy-3p0-supply = <®_3p0>;
556 fsl,anatop = <&anatop>;
560 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
563 snvs_rtc: snvs-rtc-lp {
564 compatible = "fsl,sec-v4.0-mon-rtc-lp";
571 snvs_poweroff: snvs-poweroff {
572 compatible = "syscon-poweroff";
579 snvs_pwrkey: snvs-powerkey {
580 compatible = "fsl,sec-v4.0-pwrkey";
584 wakeup-source;
589 src: reset-controller@20d8000 {
590 compatible = "fsl,imx6sll-src", "fsl,imx51-src";
594 #reset-cells = <1>;
597 gpc: interrupt-controller@20dc000 {
598 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
600 interrupt-controller;
601 #interrupt-cells = <3>;
603 interrupt-parent = <&intc>;
607 compatible = "fsl,imx6sll-iomuxc";
611 gpr: iomuxc-gpr@20e4000 {
612 compatible = "fsl,imx6sll-iomuxc-gpr",
613 "fsl,imx6q-iomuxc-gpr", "syscon";
618 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
624 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
628 sdma: dma-controller@20ec000 {
629 compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
634 clock-names = "ipg", "ahb";
635 #dma-cells = <3>;
637 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
641 compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp";
646 clock-names = "axi";
649 lcdif: lcd-controller@20f8000 {
650 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
656 clock-names = "pix", "axi", "disp_axi";
661 compatible = "fsl,imx28-dcp";
667 clock-names = "dcp";
672 compatible = "fsl,aips-bus", "simple-bus";
673 #address-cells = <1>;
674 #size-cells = <1>;
679 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
680 "fsl,imx27-usb";
686 ahb-burst-config = <0x0>;
687 tx-burst-size-dword = <0x10>;
688 rx-burst-size-dword = <0x10>;
693 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
694 "fsl,imx27-usb";
700 ahb-burst-config = <0x0>;
701 tx-burst-size-dword = <0x10>;
702 rx-burst-size-dword = <0x10>;
707 #index-cells = <1>;
708 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
709 "fsl,imx6q-usbmisc";
714 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
720 clock-names = "ipg", "ahb", "per";
721 bus-width = <4>;
722 fsl,tuning-step = <2>;
723 fsl,tuning-start-tap = <20>;
728 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
734 clock-names = "ipg", "ahb", "per";
735 bus-width = <4>;
736 fsl,tuning-step = <2>;
737 fsl,tuning-start-tap = <20>;
742 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
748 clock-names = "ipg", "ahb", "per";
749 bus-width = <4>;
750 fsl,tuning-step = <2>;
751 fsl,tuning-start-tap = <20>;
756 #address-cells = <1>;
757 #size-cells = <0>;
758 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
766 #address-cells = <1>;
767 #size-cells = <0>;
768 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
776 #address-cells = <1>;
777 #size-cells = <0>;
778 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
785 mmdc: memory-controller@21b0000 {
786 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
792 compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb";
799 #address-cells = <1>;
800 #size-cells = <1>;
801 compatible = "fsl,imx6sll-ocotp", "syscon";
805 cpu_speed_grade: speed-grade@10 {
813 tempmon_temp_grade: temp-grade@20 {
819 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
825 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
826 "fsl,imx21-uart";
830 dma-names = "rx", "tx";
833 clock-names = "ipg", "per";