Lines Matching +full:imx21 +full:- +full:wdt
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6sl-pinfunc.h"
7 #include <dt-bindings/clock/imx6sl-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
50 #address-cells = <1>;
51 #size-cells = <0>;
54 compatible = "arm,cortex-a9";
57 next-level-cache = <&L2>;
58 operating-points =
63 fsl,soc-operating-points =
64 /* ARM kHz SOC-PU uV */
68 clock-latency = <61036>; /* two CLK32 periods */
69 #cooling-cells = <2>;
73 clock-names = "arm", "pll2_pfd2_396m", "step",
75 arm-supply = <®_arm>;
76 pu-supply = <®_pu>;
77 soc-supply = <®_soc>;
78 nvmem-cells = <&cpu_speed_grade>;
79 nvmem-cell-names = "speed_grade";
85 compatible = "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <32768>;
91 compatible = "fixed-clock";
92 #clock-cells = <0>;
93 clock-frequency = <24000000>;
98 compatible = "arm,cortex-a9-pmu";
99 interrupt-parent = <&gpc>;
104 compatible = "usb-nop-xceiv";
105 #phy-cells = <0>;
109 #address-cells = <1>;
110 #size-cells = <1>;
111 compatible = "simple-bus";
112 interrupt-parent = <&gpc>;
116 compatible = "mmio-sram";
119 #address-cells = <1>;
120 #size-cells = <1>;
124 intc: interrupt-controller@a01000 {
125 compatible = "arm,cortex-a9-gic";
126 #interrupt-cells = <3>;
127 interrupt-controller;
130 interrupt-parent = <&intc>;
133 L2: cache-controller@a02000 {
134 compatible = "arm,pl310-cache";
137 cache-unified;
138 cache-level = <2>;
139 arm,tag-latency = <4 2 3>;
140 arm,data-latency = <4 2 3>;
144 compatible = "fsl,aips-bus", "simple-bus";
145 #address-cells = <1>;
146 #size-cells = <1>;
150 spba: spba-bus@2000000 {
151 compatible = "fsl,spba-bus", "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
158 compatible = "fsl,imx6sl-spdif",
159 "fsl,imx35-spdif";
164 dma-names = "rx", "tx";
170 clock-names = "core", "rxtx0",
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
186 clock-names = "ipg", "per";
191 #address-cells = <1>;
192 #size-cells = <0>;
193 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
198 clock-names = "ipg", "per";
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
210 clock-names = "ipg", "per";
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
222 clock-names = "ipg", "per";
227 compatible = "fsl,imx6sl-uart",
228 "fsl,imx6q-uart", "fsl,imx21-uart";
233 clock-names = "ipg", "per";
235 dma-names = "rx", "tx";
240 compatible = "fsl,imx6sl-uart",
241 "fsl,imx6q-uart", "fsl,imx21-uart";
246 clock-names = "ipg", "per";
248 dma-names = "rx", "tx";
253 compatible = "fsl,imx6sl-uart",
254 "fsl,imx6q-uart", "fsl,imx21-uart";
259 clock-names = "ipg", "per";
261 dma-names = "rx", "tx";
266 #sound-dai-cells = <0>;
267 compatible = "fsl,imx6sl-ssi",
268 "fsl,imx51-ssi";
273 clock-names = "ipg", "baud";
276 dma-names = "rx", "tx";
277 fsl,fifo-depth = <15>;
282 #sound-dai-cells = <0>;
283 compatible = "fsl,imx6sl-ssi",
284 "fsl,imx51-ssi";
289 clock-names = "ipg", "baud";
292 dma-names = "rx", "tx";
293 fsl,fifo-depth = <15>;
298 #sound-dai-cells = <0>;
299 compatible = "fsl,imx6sl-ssi",
300 "fsl,imx51-ssi";
305 clock-names = "ipg", "baud";
308 dma-names = "rx", "tx";
309 fsl,fifo-depth = <15>;
314 compatible = "fsl,imx6sl-uart",
315 "fsl,imx6q-uart", "fsl,imx21-uart";
320 clock-names = "ipg", "per";
322 dma-names = "rx", "tx";
327 compatible = "fsl,imx6sl-uart",
328 "fsl,imx6q-uart", "fsl,imx21-uart";
333 clock-names = "ipg", "per";
335 dma-names = "rx", "tx";
341 #pwm-cells = <3>;
342 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
347 clock-names = "ipg", "per";
351 #pwm-cells = <3>;
352 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
357 clock-names = "ipg", "per";
361 #pwm-cells = <3>;
362 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
367 clock-names = "ipg", "per";
371 #pwm-cells = <3>;
372 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
377 clock-names = "ipg", "per";
381 compatible = "fsl,imx6sl-gpt";
386 clock-names = "ipg", "per";
390 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
394 gpio-controller;
395 #gpio-cells = <2>;
396 interrupt-controller;
397 #interrupt-cells = <2>;
398 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
407 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
411 gpio-controller;
412 #gpio-cells = <2>;
413 interrupt-controller;
414 #interrupt-cells = <2>;
415 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
425 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
429 gpio-controller;
430 #gpio-cells = <2>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
433 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
444 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
448 gpio-controller;
449 #gpio-cells = <2>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
452 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
470 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
474 gpio-controller;
475 #gpio-cells = <2>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
492 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
500 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
507 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
514 clks: clock-controller@20c4000 {
515 compatible = "fsl,imx6sl-ccm";
519 #clock-cells = <1>;
523 compatible = "fsl,imx6sl-anatop",
524 "fsl,imx6q-anatop",
525 "syscon", "simple-mfd";
531 reg_vdd1p1: regulator-1p1 {
532 compatible = "fsl,anatop-regulator";
533 regulator-name = "vdd1p1";
534 regulator-min-microvolt = <1000000>;
535 regulator-max-microvolt = <1200000>;
536 regulator-always-on;
537 anatop-reg-offset = <0x110>;
538 anatop-vol-bit-shift = <8>;
539 anatop-vol-bit-width = <5>;
540 anatop-min-bit-val = <4>;
541 anatop-min-voltage = <800000>;
542 anatop-max-voltage = <1375000>;
543 anatop-enable-bit = <0>;
546 reg_vdd3p0: regulator-3p0 {
547 compatible = "fsl,anatop-regulator";
548 regulator-name = "vdd3p0";
549 regulator-min-microvolt = <2800000>;
550 regulator-max-microvolt = <3150000>;
551 regulator-always-on;
552 anatop-reg-offset = <0x120>;
553 anatop-vol-bit-shift = <8>;
554 anatop-vol-bit-width = <5>;
555 anatop-min-bit-val = <0>;
556 anatop-min-voltage = <2625000>;
557 anatop-max-voltage = <3400000>;
558 anatop-enable-bit = <0>;
561 reg_vdd2p5: regulator-2p5 {
562 compatible = "fsl,anatop-regulator";
563 regulator-name = "vdd2p5";
564 regulator-min-microvolt = <2250000>;
565 regulator-max-microvolt = <2750000>;
566 regulator-always-on;
567 anatop-reg-offset = <0x130>;
568 anatop-vol-bit-shift = <8>;
569 anatop-vol-bit-width = <5>;
570 anatop-min-bit-val = <0>;
571 anatop-min-voltage = <2100000>;
572 anatop-max-voltage = <2850000>;
573 anatop-enable-bit = <0>;
576 reg_arm: regulator-vddcore {
577 compatible = "fsl,anatop-regulator";
578 regulator-name = "vddarm";
579 regulator-min-microvolt = <725000>;
580 regulator-max-microvolt = <1450000>;
581 regulator-always-on;
582 anatop-reg-offset = <0x140>;
583 anatop-vol-bit-shift = <0>;
584 anatop-vol-bit-width = <5>;
585 anatop-delay-reg-offset = <0x170>;
586 anatop-delay-bit-shift = <24>;
587 anatop-delay-bit-width = <2>;
588 anatop-min-bit-val = <1>;
589 anatop-min-voltage = <725000>;
590 anatop-max-voltage = <1450000>;
593 reg_pu: regulator-vddpu {
594 compatible = "fsl,anatop-regulator";
595 regulator-name = "vddpu";
596 regulator-min-microvolt = <725000>;
597 regulator-max-microvolt = <1450000>;
598 anatop-reg-offset = <0x140>;
599 anatop-vol-bit-shift = <9>;
600 anatop-vol-bit-width = <5>;
601 anatop-delay-reg-offset = <0x170>;
602 anatop-delay-bit-shift = <26>;
603 anatop-delay-bit-width = <2>;
604 anatop-min-bit-val = <1>;
605 anatop-min-voltage = <725000>;
606 anatop-max-voltage = <1450000>;
609 reg_soc: regulator-vddsoc {
610 compatible = "fsl,anatop-regulator";
611 regulator-name = "vddsoc";
612 regulator-min-microvolt = <725000>;
613 regulator-max-microvolt = <1450000>;
614 regulator-always-on;
615 anatop-reg-offset = <0x140>;
616 anatop-vol-bit-shift = <18>;
617 anatop-vol-bit-width = <5>;
618 anatop-delay-reg-offset = <0x170>;
619 anatop-delay-bit-shift = <28>;
620 anatop-delay-bit-width = <2>;
621 anatop-min-bit-val = <1>;
622 anatop-min-voltage = <725000>;
623 anatop-max-voltage = <1450000>;
627 compatible = "fsl,imx6q-tempmon";
629 interrupt-parent = <&gpc>;
631 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
632 nvmem-cell-names = "calib", "temp_grade";
638 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
646 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
654 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
657 snvs_rtc: snvs-rtc-lp {
658 compatible = "fsl,sec-v4.0-mon-rtc-lp";
665 snvs_poweroff: snvs-poweroff {
666 compatible = "syscon-poweroff";
685 src: reset-controller@20d8000 {
686 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
690 #reset-cells = <1>;
694 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
696 interrupt-controller;
697 #interrupt-cells = <3>;
699 interrupt-parent = <&intc>;
701 clock-names = "ipg";
704 #address-cells = <1>;
705 #size-cells = <0>;
707 power-domain@0 {
709 #power-domain-cells = <0>;
712 pd_pu: power-domain@1 {
714 #power-domain-cells = <0>;
715 power-supply = <®_pu>;
720 pd_disp: power-domain@2 {
722 #power-domain-cells = <0>;
732 gpr: iomuxc-gpr@20e0000 {
733 compatible = "fsl,imx6sl-iomuxc-gpr",
734 "fsl,imx6q-iomuxc-gpr", "syscon";
739 compatible = "fsl,imx6sl-iomuxc";
753 sdma: dma-controller@20ec000 {
754 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
759 clock-names = "ipg", "ahb";
760 #dma-cells = <3>;
762 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
776 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
782 clock-names = "pix", "axi", "disp_axi";
784 power-domains = <&pd_disp>;
788 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
797 compatible = "fsl,aips-bus", "simple-bus";
798 #address-cells = <1>;
799 #size-cells = <1>;
804 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
810 ahb-burst-config = <0x0>;
811 tx-burst-size-dword = <0x10>;
812 rx-burst-size-dword = <0x10>;
817 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
823 ahb-burst-config = <0x0>;
824 tx-burst-size-dword = <0x10>;
825 rx-burst-size-dword = <0x10>;
830 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
838 ahb-burst-config = <0x0>;
839 tx-burst-size-dword = <0x10>;
840 rx-burst-size-dword = <0x10>;
845 #index-cells = <1>;
846 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
852 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
857 clock-names = "ipg", "ahb";
862 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
868 clock-names = "ipg", "ahb", "per";
869 bus-width = <4>;
874 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
880 clock-names = "ipg", "ahb", "per";
881 bus-width = <4>;
886 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
892 clock-names = "ipg", "ahb", "per";
893 bus-width = <4>;
898 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
904 clock-names = "ipg", "ahb", "per";
905 bus-width = <4>;
910 #address-cells = <1>;
911 #size-cells = <0>;
912 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
920 #address-cells = <1>;
921 #size-cells = <0>;
922 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
930 #address-cells = <1>;
931 #size-cells = <0>;
932 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
939 memory-controller@21b0000 {
940 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
946 compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
952 weim: memory-controller@21b8000 {
953 #address-cells = <2>;
954 #size-cells = <1>;
957 fsl,weim-cs-gpr = <&gpr>;
962 compatible = "fsl,imx6sl-ocotp", "syscon";
965 #address-cells = <1>;
966 #size-cells = <1>;
968 cpu_speed_grade: speed-grade@10 {
976 tempmon_temp_grade: temp-grade@20 {
982 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
994 clock-names = "bus", "core";
995 power-domains = <&pd_pu>;
1004 clock-names = "bus", "core";
1005 power-domains = <&pd_pu>;