Lines Matching +full:aips +full:- +full:bus
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <24000000>;
77 #address-cells = <1>;
78 #size-cells = <0>;
79 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
83 lvds-channel@0 {
84 #address-cells = <1>;
85 #size-cells = <0>;
93 remote-endpoint = <&ipu1_di0_lvds0>;
101 remote-endpoint = <&ipu1_di1_lvds0>;
106 lvds-channel@1 {
107 #address-cells = <1>;
108 #size-cells = <0>;
116 remote-endpoint = <&ipu1_di0_lvds1>;
124 remote-endpoint = <&ipu1_di1_lvds1>;
131 compatible = "arm,cortex-a9-pmu";
132 interrupt-parent = <&gpc>;
137 compatible = "usb-nop-xceiv";
138 #phy-cells = <0>;
142 compatible = "usb-nop-xceiv";
143 #phy-cells = <0>;
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "simple-bus";
150 interrupt-parent = <&gpc>;
153 dma_apbh: dma-controller@110000 {
154 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
160 #dma-cells = <1>;
161 dma-channels = <4>;
165 gpmi: nand-controller@112000 {
166 compatible = "fsl,imx6q-gpmi-nand";
168 reg-names = "gpmi-nand", "bch";
170 interrupt-names = "bch";
176 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
179 dma-names = "rx-tx";
189 clock-names = "iahb", "isfr";
193 #address-cells = <1>;
194 #size-cells = <0>;
200 remote-endpoint = <&ipu1_di0_hdmi>;
208 remote-endpoint = <&ipu1_di1_hdmi>;
221 clock-names = "bus", "core", "shader";
222 power-domains = <&pd_pu>;
223 #cooling-cells = <2>;
232 clock-names = "bus", "core";
233 power-domains = <&pd_pu>;
234 #cooling-cells = <2>;
238 compatible = "arm,cortex-a9-twd-timer";
241 interrupt-parent = <&intc>;
245 intc: interrupt-controller@a01000 {
246 compatible = "arm,cortex-a9-gic";
247 #interrupt-cells = <3>;
248 interrupt-controller;
251 interrupt-parent = <&intc>;
254 L2: cache-controller@a02000 {
255 compatible = "arm,pl310-cache";
258 cache-unified;
259 cache-level = <2>;
260 arm,tag-latency = <4 2 3>;
261 arm,data-latency = <4 2 3>;
262 arm,shared-override;
266 compatible = "fsl,imx6q-pcie";
269 reg-names = "dbi", "config";
270 #address-cells = <3>;
271 #size-cells = <2>;
273 bus-range = <0x00 0xff>;
275 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
276 num-lanes = <1>;
278 interrupt-names = "msi";
279 #interrupt-cells = <1>;
280 interrupt-map-mask = <0 0 0 0x7>;
281 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
288 clock-names = "pcie", "pcie_bus", "pcie_phy";
292 aips1: bus@2000000 { /* AIPS1 */
293 compatible = "fsl,aips-bus", "simple-bus";
294 #address-cells = <1>;
295 #size-cells = <1>;
299 spba-bus@2000000 {
300 compatible = "fsl,spba-bus", "simple-bus";
301 #address-cells = <1>;
302 #size-cells = <1>;
307 compatible = "fsl,imx35-spdif";
312 dma-names = "rx", "tx";
318 clock-names = "core", "rxtx0",
327 #address-cells = <1>;
328 #size-cells = <0>;
329 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
334 clock-names = "ipg", "per";
336 dma-names = "rx", "tx";
341 #address-cells = <1>;
342 #size-cells = <0>;
343 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
348 clock-names = "ipg", "per";
350 dma-names = "rx", "tx";
355 #address-cells = <1>;
356 #size-cells = <0>;
357 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
362 clock-names = "ipg", "per";
364 dma-names = "rx", "tx";
369 #address-cells = <1>;
370 #size-cells = <0>;
371 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
376 clock-names = "ipg", "per";
378 dma-names = "rx", "tx";
383 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
388 clock-names = "ipg", "per";
390 dma-names = "rx", "tx";
395 #sound-dai-cells = <0>;
396 compatible = "fsl,imx35-esai";
403 clock-names = "core", "extal", "fsys", "spba";
405 dma-names = "rx", "tx";
410 #sound-dai-cells = <0>;
411 compatible = "fsl,imx6q-ssi",
412 "fsl,imx51-ssi";
417 clock-names = "ipg", "baud";
420 dma-names = "rx", "tx";
421 fsl,fifo-depth = <15>;
426 #sound-dai-cells = <0>;
427 compatible = "fsl,imx6q-ssi",
428 "fsl,imx51-ssi";
433 clock-names = "ipg", "baud";
436 dma-names = "rx", "tx";
437 fsl,fifo-depth = <15>;
442 #sound-dai-cells = <0>;
443 compatible = "fsl,imx6q-ssi",
444 "fsl,imx51-ssi";
449 clock-names = "ipg", "baud";
452 dma-names = "rx", "tx";
453 fsl,fifo-depth = <15>;
458 compatible = "fsl,imx53-asrc";
468 clock-names = "mem", "ipg", "asrck_0",
475 dma-names = "rxa", "rxb", "rxc",
477 fsl,asrc-rate = <48000>;
478 fsl,asrc-width = <16>;
482 spba-bus@203c000 {
492 interrupt-names = "bit", "jpeg";
495 clock-names = "per", "ahb";
496 power-domains = <&pd_pu>;
506 #pwm-cells = <3>;
507 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
512 clock-names = "ipg", "per";
517 #pwm-cells = <3>;
518 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
523 clock-names = "ipg", "per";
528 #pwm-cells = <3>;
529 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
534 clock-names = "ipg", "per";
539 #pwm-cells = <3>;
540 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
545 clock-names = "ipg", "per";
550 compatible = "fsl,imx6q-flexcan";
555 clock-names = "ipg", "per";
556 fsl,stop-mode = <&gpr 0x34 28>;
561 compatible = "fsl,imx6q-flexcan";
566 clock-names = "ipg", "per";
567 fsl,stop-mode = <&gpr 0x34 29>;
572 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
578 clock-names = "ipg", "per", "osc_per";
582 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
586 gpio-controller;
587 #gpio-cells = <2>;
588 interrupt-controller;
589 #interrupt-cells = <2>;
593 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
597 gpio-controller;
598 #gpio-cells = <2>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
604 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
608 gpio-controller;
609 #gpio-cells = <2>;
610 interrupt-controller;
611 #interrupt-cells = <2>;
615 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
619 gpio-controller;
620 #gpio-cells = <2>;
621 interrupt-controller;
622 #interrupt-cells = <2>;
626 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
630 gpio-controller;
631 #gpio-cells = <2>;
632 interrupt-controller;
633 #interrupt-cells = <2>;
637 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
641 gpio-controller;
642 #gpio-cells = <2>;
643 interrupt-controller;
644 #interrupt-cells = <2>;
648 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
652 gpio-controller;
653 #gpio-cells = <2>;
654 interrupt-controller;
655 #interrupt-cells = <2>;
659 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
667 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
674 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
681 clks: clock-controller@20c4000 {
682 compatible = "fsl,imx6q-ccm";
686 #clock-cells = <1>;
690 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
696 reg_vdd1p1: regulator-1p1 {
697 compatible = "fsl,anatop-regulator";
698 regulator-name = "vdd1p1";
699 regulator-min-microvolt = <1000000>;
700 regulator-max-microvolt = <1200000>;
701 regulator-always-on;
702 anatop-reg-offset = <0x110>;
703 anatop-vol-bit-shift = <8>;
704 anatop-vol-bit-width = <5>;
705 anatop-min-bit-val = <4>;
706 anatop-min-voltage = <800000>;
707 anatop-max-voltage = <1375000>;
708 anatop-enable-bit = <0>;
711 reg_vdd3p0: regulator-3p0 {
712 compatible = "fsl,anatop-regulator";
713 regulator-name = "vdd3p0";
714 regulator-min-microvolt = <2800000>;
715 regulator-max-microvolt = <3150000>;
716 regulator-always-on;
717 anatop-reg-offset = <0x120>;
718 anatop-vol-bit-shift = <8>;
719 anatop-vol-bit-width = <5>;
720 anatop-min-bit-val = <0>;
721 anatop-min-voltage = <2625000>;
722 anatop-max-voltage = <3400000>;
723 anatop-enable-bit = <0>;
726 reg_vdd2p5: regulator-2p5 {
727 compatible = "fsl,anatop-regulator";
728 regulator-name = "vdd2p5";
729 regulator-min-microvolt = <2250000>;
730 regulator-max-microvolt = <2750000>;
731 regulator-always-on;
732 anatop-reg-offset = <0x130>;
733 anatop-vol-bit-shift = <8>;
734 anatop-vol-bit-width = <5>;
735 anatop-min-bit-val = <0>;
736 anatop-min-voltage = <2100000>;
737 anatop-max-voltage = <2875000>;
738 anatop-enable-bit = <0>;
741 reg_arm: regulator-vddcore {
742 compatible = "fsl,anatop-regulator";
743 regulator-name = "vddarm";
744 regulator-min-microvolt = <725000>;
745 regulator-max-microvolt = <1450000>;
746 regulator-always-on;
747 anatop-reg-offset = <0x140>;
748 anatop-vol-bit-shift = <0>;
749 anatop-vol-bit-width = <5>;
750 anatop-delay-reg-offset = <0x170>;
751 anatop-delay-bit-shift = <24>;
752 anatop-delay-bit-width = <2>;
753 anatop-min-bit-val = <1>;
754 anatop-min-voltage = <725000>;
755 anatop-max-voltage = <1450000>;
758 reg_pu: regulator-vddpu {
759 compatible = "fsl,anatop-regulator";
760 regulator-name = "vddpu";
761 regulator-min-microvolt = <725000>;
762 regulator-max-microvolt = <1450000>;
763 regulator-enable-ramp-delay = <380>;
764 anatop-reg-offset = <0x140>;
765 anatop-vol-bit-shift = <9>;
766 anatop-vol-bit-width = <5>;
767 anatop-delay-reg-offset = <0x170>;
768 anatop-delay-bit-shift = <26>;
769 anatop-delay-bit-width = <2>;
770 anatop-min-bit-val = <1>;
771 anatop-min-voltage = <725000>;
772 anatop-max-voltage = <1450000>;
775 reg_soc: regulator-vddsoc {
776 compatible = "fsl,anatop-regulator";
777 regulator-name = "vddsoc";
778 regulator-min-microvolt = <725000>;
779 regulator-max-microvolt = <1450000>;
780 regulator-always-on;
781 anatop-reg-offset = <0x140>;
782 anatop-vol-bit-shift = <18>;
783 anatop-vol-bit-width = <5>;
784 anatop-delay-reg-offset = <0x170>;
785 anatop-delay-bit-shift = <28>;
786 anatop-delay-bit-width = <2>;
787 anatop-min-bit-val = <1>;
788 anatop-min-voltage = <725000>;
789 anatop-max-voltage = <1450000>;
793 compatible = "fsl,imx6q-tempmon";
794 interrupt-parent = <&gpc>;
797 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
798 nvmem-cell-names = "calib", "temp_grade";
800 #thermal-sensor-cells = <0>;
805 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
813 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
821 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
824 snvs_rtc: snvs-rtc-lp {
825 compatible = "fsl,sec-v4.0-mon-rtc-lp";
832 snvs_poweroff: snvs-poweroff {
833 compatible = "syscon-poweroff";
841 snvs_pwrkey: snvs-powerkey {
842 compatible = "fsl,sec-v4.0-pwrkey";
846 wakeup-source;
850 snvs_lpgpr: snvs-lpgpr {
851 compatible = "fsl,imx6q-snvs-lpgpr";
865 src: reset-controller@20d8000 {
866 compatible = "fsl,imx6q-src", "fsl,imx51-src";
870 #reset-cells = <1>;
874 compatible = "fsl,imx6q-gpc";
876 interrupt-controller;
877 #interrupt-cells = <3>;
879 interrupt-parent = <&intc>;
881 clock-names = "ipg";
884 #address-cells = <1>;
885 #size-cells = <0>;
887 power-domain@0 {
889 #power-domain-cells = <0>;
891 pd_pu: power-domain@1 {
893 #power-domain-cells = <0>;
894 power-supply = <®_pu>;
905 gpr: iomuxc-gpr@20e0000 {
906 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
909 mux: mux-controller {
910 compatible = "mmio-mux";
911 #mux-control-cells = <1>;
916 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
930 sdma: dma-controller@20ec000 {
931 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
936 clock-names = "ipg", "ahb";
937 #dma-cells = <3>;
938 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
942 aips2: bus@2100000 { /* AIPS2 */
943 compatible = "fsl,aips-bus", "simple-bus";
944 #address-cells = <1>;
945 #size-cells = <1>;
950 compatible = "fsl,sec-v4.0";
951 #address-cells = <1>;
952 #size-cells = <1>;
959 clock-names = "mem", "aclk", "ipg", "emi_slow";
962 compatible = "fsl,sec-v4.0-job-ring";
968 compatible = "fsl,sec-v4.0-job-ring";
979 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
985 ahb-burst-config = <0x0>;
986 tx-burst-size-dword = <0x10>;
987 rx-burst-size-dword = <0x10>;
992 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
999 ahb-burst-config = <0x0>;
1000 tx-burst-size-dword = <0x10>;
1001 rx-burst-size-dword = <0x10>;
1006 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1014 ahb-burst-config = <0x0>;
1015 tx-burst-size-dword = <0x10>;
1016 rx-burst-size-dword = <0x10>;
1021 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1029 ahb-burst-config = <0x0>;
1030 tx-burst-size-dword = <0x10>;
1031 rx-burst-size-dword = <0x10>;
1036 #index-cells = <1>;
1037 compatible = "fsl,imx6q-usbmisc";
1043 compatible = "fsl,imx6q-fec";
1045 interrupt-names = "int0", "pps";
1052 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
1053 fsl,stop-mode = <&gpr 0x34 27>;
1054 nvmem-cells = <&fec_mac_addr>;
1055 nvmem-cell-names = "mac-address";
1067 compatible = "fsl,imx6q-usdhc";
1073 clock-names = "ipg", "ahb", "per";
1074 bus-width = <4>;
1079 compatible = "fsl,imx6q-usdhc";
1085 clock-names = "ipg", "ahb", "per";
1086 bus-width = <4>;
1091 compatible = "fsl,imx6q-usdhc";
1097 clock-names = "ipg", "ahb", "per";
1098 bus-width = <4>;
1103 compatible = "fsl,imx6q-usdhc";
1109 clock-names = "ipg", "ahb", "per";
1110 bus-width = <4>;
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1117 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1127 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1137 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1148 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1149 compatible = "fsl,imx6q-mmdc";
1154 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1155 compatible = "fsl,imx6q-mmdc";
1160 weim: memory-controller@21b8000 {
1161 #address-cells = <2>;
1162 #size-cells = <1>;
1163 compatible = "fsl,imx6q-weim";
1167 fsl,weim-cs-gpr = <&gpr>;
1172 compatible = "fsl,imx6q-ocotp", "syscon";
1175 #address-cells = <1>;
1176 #size-cells = <1>;
1178 cpu_speed_grade: speed-grade@10 {
1186 tempmon_temp_grade: temp-grade@20 {
1190 fec_mac_addr: mac-addr@88 {
1206 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1212 compatible = "fsl,imx6-mipi-csi2";
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1220 clock-names = "dphy", "ref", "pix";
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1236 remote-endpoint = <&ipu1_di0_mipi>;
1244 remote-endpoint = <&ipu1_di1_mipi>;
1251 compatible = "fsl,imx6q-vdoa";
1258 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1263 clock-names = "ipg", "per";
1265 dma-names = "rx", "tx";
1270 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1275 clock-names = "ipg", "per";
1277 dma-names = "rx", "tx";
1282 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1287 clock-names = "ipg", "per";
1289 dma-names = "rx", "tx";
1294 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1299 clock-names = "ipg", "per";
1301 dma-names = "rx", "tx";
1307 #address-cells = <1>;
1308 #size-cells = <0>;
1309 compatible = "fsl,imx6q-ipu";
1316 clock-names = "bus", "di0", "di1";
1323 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1342 remote-endpoint = <&hdmi_mux_0>;
1347 remote-endpoint = <&mipi_mux_0>;
1352 remote-endpoint = <&lvds0_mux_0>;
1357 remote-endpoint = <&lvds1_mux_0>;
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1372 remote-endpoint = <&hdmi_mux_1>;
1377 remote-endpoint = <&mipi_mux_1>;
1382 remote-endpoint = <&lvds0_mux_1>;
1387 remote-endpoint = <&lvds1_mux_1>;