Lines Matching +full:0 +full:x20e0000
59 #clock-cells = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 #size-cells = <0>;
83 lvds-channel@0 {
85 #size-cells = <0>;
86 reg = <0>;
89 port@0 {
90 reg = <0>;
108 #size-cells = <0>;
112 port@0 {
113 reg = <0>;
133 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
138 #phy-cells = <0>;
143 #phy-cells = <0>;
155 reg = <0x00110000 0x2000>;
156 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
157 <0 13 IRQ_TYPE_LEVEL_HIGH>,
158 <0 13 IRQ_TYPE_LEVEL_HIGH>,
159 <0 13 IRQ_TYPE_LEVEL_HIGH>;
167 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
169 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
178 dmas = <&dma_apbh 0>;
184 reg = <0x00120000 0x9000>;
185 interrupts = <0 115 0x04>;
194 #size-cells = <0>;
196 port@0 {
197 reg = <0>;
216 reg = <0x00130000 0x4000>;
217 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
228 reg = <0x00134000 0x4000>;
229 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
239 reg = <0x00a00600 0x20>;
240 interrupts = <1 13 0xf01>;
249 reg = <0x00a01000 0x1000>,
250 <0x00a00100 0x100>;
256 reg = <0x00a02000 0x1000>;
257 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
267 reg = <0x01ffc000 0x04000>,
268 <0x01f00000 0x80000>;
273 bus-range = <0x00 0xff>;
274 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */
275 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
280 interrupt-map-mask = <0 0 0 0x7>;
281 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
282 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
283 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
284 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
296 reg = <0x02000000 0x100000>;
303 reg = <0x02000000 0x40000>;
308 reg = <0x02004000 0x4000>;
309 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
310 dmas = <&sdma 14 18 0>,
311 <&sdma 15 18 0>;
328 #size-cells = <0>;
330 reg = <0x02008000 0x4000>;
331 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
342 #size-cells = <0>;
344 reg = <0x0200c000 0x4000>;
345 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
356 #size-cells = <0>;
358 reg = <0x02010000 0x4000>;
359 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
370 #size-cells = <0>;
372 reg = <0x02014000 0x4000>;
373 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
384 reg = <0x02020000 0x4000>;
385 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
389 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
395 #sound-dai-cells = <0>;
397 reg = <0x02024000 0x4000>;
398 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
404 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
410 #sound-dai-cells = <0>;
413 reg = <0x02028000 0x4000>;
414 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
418 dmas = <&sdma 37 1 0>,
419 <&sdma 38 1 0>;
426 #sound-dai-cells = <0>;
429 reg = <0x0202c000 0x4000>;
430 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
434 dmas = <&sdma 41 1 0>,
435 <&sdma 42 1 0>;
442 #sound-dai-cells = <0>;
445 reg = <0x02030000 0x4000>;
446 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
450 dmas = <&sdma 45 1 0>,
451 <&sdma 46 1 0>;
459 reg = <0x02034000 0x4000>;
460 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
462 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
463 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
464 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
465 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
466 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
483 reg = <0x0203c000 0x4000>;
489 reg = <0x02040000 0x3c000>;
490 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
491 <0 3 IRQ_TYPE_LEVEL_HIGH>;
502 reg = <0x0207c000 0x4000>;
508 reg = <0x02080000 0x4000>;
509 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
519 reg = <0x02084000 0x4000>;
520 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
530 reg = <0x02088000 0x4000>;
531 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
541 reg = <0x0208c000 0x4000>;
542 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
551 reg = <0x02090000 0x4000>;
552 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
556 fsl,stop-mode = <&gpr 0x34 28>;
562 reg = <0x02094000 0x4000>;
563 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
567 fsl,stop-mode = <&gpr 0x34 29>;
573 reg = <0x02098000 0x4000>;
574 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
583 reg = <0x0209c000 0x4000>;
584 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
585 <0 67 IRQ_TYPE_LEVEL_HIGH>;
594 reg = <0x020a0000 0x4000>;
595 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
596 <0 69 IRQ_TYPE_LEVEL_HIGH>;
605 reg = <0x020a4000 0x4000>;
606 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
607 <0 71 IRQ_TYPE_LEVEL_HIGH>;
616 reg = <0x020a8000 0x4000>;
617 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
618 <0 73 IRQ_TYPE_LEVEL_HIGH>;
627 reg = <0x020ac000 0x4000>;
628 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
629 <0 75 IRQ_TYPE_LEVEL_HIGH>;
638 reg = <0x020b0000 0x4000>;
639 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
640 <0 77 IRQ_TYPE_LEVEL_HIGH>;
649 reg = <0x020b4000 0x4000>;
650 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
651 <0 79 IRQ_TYPE_LEVEL_HIGH>;
660 reg = <0x020b8000 0x4000>;
661 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
668 reg = <0x020bc000 0x4000>;
669 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
675 reg = <0x020c0000 0x4000>;
676 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
683 reg = <0x020c4000 0x4000>;
684 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
685 <0 88 IRQ_TYPE_LEVEL_HIGH>;
691 reg = <0x020c8000 0x1000>;
692 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
693 <0 54 IRQ_TYPE_LEVEL_HIGH>,
694 <0 127 IRQ_TYPE_LEVEL_HIGH>;
702 anatop-reg-offset = <0x110>;
708 anatop-enable-bit = <0>;
717 anatop-reg-offset = <0x120>;
720 anatop-min-bit-val = <0>;
723 anatop-enable-bit = <0>;
732 anatop-reg-offset = <0x130>;
735 anatop-min-bit-val = <0>;
738 anatop-enable-bit = <0>;
747 anatop-reg-offset = <0x140>;
748 anatop-vol-bit-shift = <0>;
750 anatop-delay-reg-offset = <0x170>;
764 anatop-reg-offset = <0x140>;
767 anatop-delay-reg-offset = <0x170>;
781 anatop-reg-offset = <0x140>;
784 anatop-delay-reg-offset = <0x170>;
795 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
800 #thermal-sensor-cells = <0>;
806 reg = <0x020c9000 0x1000>;
807 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
814 reg = <0x020ca000 0x1000>;
815 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
821 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
822 reg = <0x020cc000 0x4000>;
825 compatible = "fsl,sec-v4.0-mon-rtc-lp";
827 offset = <0x34>;
828 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
829 <0 20 IRQ_TYPE_LEVEL_HIGH>;
835 offset = <0x38>;
836 value = <0x60>;
837 mask = <0x60>;
842 compatible = "fsl,sec-v4.0-pwrkey";
856 reg = <0x020d0000 0x4000>;
857 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
861 reg = <0x020d4000 0x4000>;
862 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
867 reg = <0x020d8000 0x4000>;
868 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
869 <0 96 IRQ_TYPE_LEVEL_HIGH>;
875 reg = <0x020dc000 0x4000>;
878 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
885 #size-cells = <0>;
887 power-domain@0 {
888 reg = <0>;
889 #power-domain-cells = <0>;
893 #power-domain-cells = <0>;
907 reg = <0x20e0000 0x38>;
917 reg = <0x20e0000 0x4000>;
921 reg = <0x020e4000 0x4000>;
922 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
926 reg = <0x020e8000 0x4000>;
927 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
932 reg = <0x020ec000 0x4000>;
933 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
946 reg = <0x02100000 0x100000>;
950 compatible = "fsl,sec-v4.0";
953 reg = <0x2100000 0x10000>;
954 ranges = <0 0x2100000 0x10000>;
962 compatible = "fsl,sec-v4.0-job-ring";
963 reg = <0x1000 0x1000>;
968 compatible = "fsl,sec-v4.0-job-ring";
969 reg = <0x2000 0x1000>;
975 reg = <0x0217c000 0x4000>;
980 reg = <0x02184000 0x200>;
981 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
984 fsl,usbmisc = <&usbmisc 0>;
985 ahb-burst-config = <0x0>;
986 tx-burst-size-dword = <0x10>;
987 rx-burst-size-dword = <0x10>;
993 reg = <0x02184200 0x200>;
994 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
999 ahb-burst-config = <0x0>;
1000 tx-burst-size-dword = <0x10>;
1001 rx-burst-size-dword = <0x10>;
1007 reg = <0x02184400 0x200>;
1008 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1014 ahb-burst-config = <0x0>;
1015 tx-burst-size-dword = <0x10>;
1016 rx-burst-size-dword = <0x10>;
1022 reg = <0x02184600 0x200>;
1023 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1029 ahb-burst-config = <0x0>;
1030 tx-burst-size-dword = <0x10>;
1031 rx-burst-size-dword = <0x10>;
1038 reg = <0x02184800 0x200>;
1044 reg = <0x02188000 0x4000>;
1046 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1047 <0 119 IRQ_TYPE_LEVEL_HIGH>;
1053 fsl,stop-mode = <&gpr 0x34 27>;
1060 reg = <0x0218c000 0x4000>;
1061 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1062 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1063 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1068 reg = <0x02190000 0x4000>;
1069 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1080 reg = <0x02194000 0x4000>;
1081 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1092 reg = <0x02198000 0x4000>;
1093 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1104 reg = <0x0219c000 0x4000>;
1105 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1116 #size-cells = <0>;
1118 reg = <0x021a0000 0x4000>;
1119 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1126 #size-cells = <0>;
1128 reg = <0x021a4000 0x4000>;
1129 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1136 #size-cells = <0>;
1138 reg = <0x021a8000 0x4000>;
1139 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1145 reg = <0x021ac000 0x4000>;
1150 reg = <0x021b0000 0x4000>;
1156 reg = <0x021b4000 0x4000>;
1164 reg = <0x021b8000 0x4000>;
1165 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1173 reg = <0x021bc000 0x4000>;
1179 reg = <0x10 4>;
1183 reg = <0x38 4>;
1187 reg = <0x20 4>;
1191 reg = <0x88 6>;
1196 reg = <0x021d0000 0x4000>;
1197 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1201 reg = <0x021d4000 0x4000>;
1202 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1207 reg = <0x021d8000 0x4000>;
1213 reg = <0x021dc000 0x4000>;
1215 #size-cells = <0>;
1216 interrupts = <0 100 0x04>, <0 101 0x04>;
1225 reg = <0x021e0000 0x4000>;
1230 #size-cells = <0>;
1232 port@0 {
1233 reg = <0>;
1252 reg = <0x021e4000 0x4000>;
1253 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1259 reg = <0x021e8000 0x4000>;
1260 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1264 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1271 reg = <0x021ec000 0x4000>;
1272 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1276 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1283 reg = <0x021f0000 0x4000>;
1284 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1295 reg = <0x021f4000 0x4000>;
1296 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1300 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1308 #size-cells = <0>;
1310 reg = <0x02400000 0x400000>;
1311 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1312 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1319 ipu1_csi0: port@0 {
1320 reg = <0>;
1333 #size-cells = <0>;
1336 ipu1_di0_disp0: endpoint@0 {
1337 reg = <0>;
1363 #size-cells = <0>;
1366 ipu1_di1_disp1: endpoint@0 {
1367 reg = <0>;