Lines Matching +full:0 +full:x1b0b1
66 reg = <0x10000000 0>; /* will be filled by U-Boot */
71 #size-cells = <0>;
75 #clock-cells = <0>;
97 pinctrl-0 = <&pinctrl_user_led>;
109 pinctrl-0 = <&pinctrl_etnphy_power>;
136 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
146 pinctrl-0 = <&pinctrl_lcd0_pwr>;
158 pinctrl-0 = <&pinctrl_lcd1_pwr>;
170 pinctrl-0 = <&pinctrl_usbh1_vbus>;
181 pinctrl-0 = <&pinctrl_usbotg_vbus>;
191 pinctrl-0 = <&pinctrl_audmux>;
219 fsl,audmux-port = <0>;
234 IMX_AUDMUX_V2_PDCR_RXDSEL(0)
241 pinctrl-0 = <&pinctrl_flexcan1>;
248 pinctrl-0 = <&pinctrl_flexcan2>;
255 pinctrl-0 = <&pinctrl_ecspi1>;
265 pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>;
275 #size-cells = <0>;
277 etnphy: ethernet-phy@0 {
279 reg = <0>;
281 pinctrl-0 = <&pinctrl_etnphy_int>;
290 pinctrl-0 = <&pinctrl_gpmi_nand>;
298 pinctrl-0 = <&pinctrl_i2c1>;
307 reg = <0x68>;
315 pinctrl-0 = <&pinctrl_i2c3>;
324 #sound-dai-cells = <0>;
325 reg = <0x0a>;
333 reg = <0x38>;
335 pinctrl-0 = <&pinctrl_edt_ft5x06>;
345 reg = <0x48>;
347 pinctrl-0 = <&pinctrl_tsc2007>;
349 interrupts = <26 0>;
358 pinctrl-0 = <&pinctrl_hog>;
362 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
368 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
369 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
370 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
371 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
377 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
378 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
379 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
380 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
382 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
383 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
384 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
385 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
386 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
387 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
388 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
389 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
390 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
391 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
392 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
393 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
394 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
395 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
396 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
397 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
398 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
399 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
400 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
401 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
402 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
403 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
404 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
410 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
411 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
412 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
413 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
414 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
415 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
416 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
417 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
418 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
419 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
420 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
421 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
422 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
423 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
424 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
425 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
426 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
427 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
428 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
429 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
430 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
431 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
432 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
433 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
434 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
435 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
436 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
437 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
443 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
444 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
445 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
446 MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
447 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
448 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
454 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
455 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
456 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
462 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
463 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
464 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
465 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
466 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
467 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
468 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
474 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
475 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
481 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
487 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
493 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
499 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
500 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
506 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
507 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
513 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
519 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
520 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
521 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
522 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
523 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
524 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
525 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
526 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
527 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
528 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
529 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
530 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
531 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
532 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
533 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
539 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
540 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
546 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
547 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
553 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
554 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
560 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
561 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
567 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
568 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
569 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
570 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
571 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
572 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
573 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
574 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
580 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
586 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
592 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
598 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
604 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
610 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
611 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
617 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
618 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
624 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
625 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
631 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
632 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
638 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
639 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
645 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
646 MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
652 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
658 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
664 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
670 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
671 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
672 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
673 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
674 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
675 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
676 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
682 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
683 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
684 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
685 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
686 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
687 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
688 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
694 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
701 pinctrl-0 = <&pinctrl_kpp>;
703 /* row/col 0,1 are mapped to KPP row/col 6,7 */
705 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
706 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
707 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
708 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
709 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
710 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
711 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
712 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
713 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
714 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
715 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
722 pinctrl-0 = <&pinctrl_pwm1>;
728 pinctrl-0 = <&pinctrl_pwm2>;
738 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
745 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
752 pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
767 pinctrl-0 = <&pinctrl_usbotg>;
775 pinctrl-0 = <&pinctrl_usdhc1>;
785 pinctrl-0 = <&pinctrl_usdhc2>;