Lines Matching +full:0 +full:x1b0b1
49 pwms = <&pwm1 0 5000000 0>;
50 brightness-levels = <0 4 8 16 32 64 128 255>;
74 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
76 pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>;
87 pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>;
96 pinctrl-0 = <&pinctrl_audmux>;
102 pinctrl-0 = <&pinctrl_flexcan1>;
108 pinctrl-0 = <&pinctrl_flexcan2>;
117 pinctrl-0 = <&pinctrl_ecspi1>;
124 pinctrl-0 = <&pinctrl_ecspi2>;
131 pinctrl-0 = <&pinctrl_ecspi4>;
145 pinctrl-0 = <&pinctrl_i2c1>;
150 reg = <0x58>;
152 interrupts = <04 0x8>;
271 reg = <0x71>;
277 pinctrl-0 = <&pinctrl_i2c2>;
283 pinctrl-0 = <&pinctrl_i2c3>;
288 reg = <0x20>;
295 reg = <0x68>;
301 pinctrl-0 = <&pinctrl_i2c4>;
306 reg = <0x50>;
311 reg = <0x57>;
317 pinctrl-0 = <&pinctrl_enet>;
325 #size-cells = <0>;
329 txd0-skew-ps = <0>;
330 txd1-skew-ps = <0>;
331 txd2-skew-ps = <0>;
332 txd3-skew-ps = <0>;
339 pinctrl-0 = <&pinctrl_gpmi_nand>;
350 pinctrl-0 = <&pinctrl_pwm1>;
356 pinctrl-0 = <&pinctrl_uart1>;
363 pinctrl-0 = <&pinctrl_uart2>;
369 pinctrl-0 = <&pinctrl_uart3>;
376 pinctrl-0 = <&pinctrl_uart4>;
389 pinctrl-0 = <&pinctrl_usbotg>;
397 pinctrl-0 = <&pinctrl_usdhc1>;
405 pinctrl-0 = <&pinctrl_usdhc2>;
414 pinctrl-0 = <&pinctrl_gpio>;
418 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
419 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
420 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
421 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
427 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
428 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
429 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
430 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */
431 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */
432 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */
438 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
439 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
440 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
441 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */
442 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */
448 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
449 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
450 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
451 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
452 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
453 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */
459 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
460 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
461 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
462 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
463 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
464 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
465 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
466 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
467 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
468 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
469 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
470 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
471 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
472 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
473 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
479 MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
480 MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
486 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
487 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
493 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* led enable */
494 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* LCD power enable */
495 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* led yellow */
496 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 /* led red */
497 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /* led green */
498 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 /* led blue */
499 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* Profibus IRQ */
500 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* FPGA IRQ */
501 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /* spi bus #2 SS driver enable */
502 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 /* RST_LOC# PHY reset input (has pull-down!)*/
503 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0 /* USB_OTG_ID = GPIO1_24*/
504 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* Touchscreen IRQ */
505 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 /* PCIe reset */
511 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
512 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
513 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
514 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
515 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
516 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
517 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
518 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
519 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
520 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
521 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
522 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
523 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
524 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
525 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
531 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
532 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
538 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
539 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
545 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
546 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
552 MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
553 MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
559 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0
560 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 /* backlight enable */
566 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
567 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
568 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
569 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
575 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
576 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
582 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
583 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
584 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
585 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
591 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
592 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
598 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
603 fsl,pins = <MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x130b0>;
607 fsl,pins = <MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0>;
612 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
613 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
614 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
615 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
616 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
617 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
618 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 /* SD1 card detect input */
619 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* SD1 write protect input */
625 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71
626 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71
627 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
628 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
629 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
630 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
631 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 /* SD2 level shifter output enable */
632 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* SD2 card detect input */
633 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SD2 write protect input */