Lines Matching +full:0 +full:x130b0
28 pinctrl-0 = <&pinctrl_enet>;
37 #size-cells = <0>;
52 pinctrl-0 = <&pinctrl_uart2>;
60 pinctrl-0 = <&pinctrl_usdhc1>;
71 #size-cells = <0>;
85 pinctrl-0 = <&pinctrl_usdhc3>;
95 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
96 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
97 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
98 MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
99 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0
100 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
101 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
102 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
103 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
104 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
105 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
106 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
107 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
108 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
109 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030
110 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030
111 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
117 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0
118 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0
119 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0
120 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0
121 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */
127 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
128 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
129 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
130 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
131 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
132 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
133 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x130b0 /* WL_EN */
134 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x130b0 /* WL_IRQ */
140 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
141 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
142 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
143 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
144 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
145 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
146 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
147 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
148 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
149 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059