Lines Matching +full:0 +full:x5
60 pinctrl-0 = <&pinctrl_rgb24_vga1>;
80 hsync-active = <0>;
81 vsync-active = <0>;
83 pixelclk-active = <0>;
96 hsync-active = <0>;
97 vsync-active = <0>;
99 pixelclk-active = <0>;
112 hsync-active = <0>;
113 vsync-active = <0>;
115 pixelclk-active = <0>;
128 hsync-active = <0>;
129 vsync-active = <0>;
144 hsync-active = <0>;
145 vsync-active = <0>;
147 pixelclk-active = <0>;
160 hsync-active = <0>;
161 vsync-active = <0>;
163 pixelclk-active = <0>;
176 hsync-active = <0>;
177 vsync-active = <0>;
179 pixelclk-active = <0>;
186 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
189 0 1 2 3 4 5 6 7 8 9
227 pinctrl-0 = <&pinctrl_i2c3>;
232 reg = <0x0a>;
233 #sound-dai-cells = <0>;
241 reg = <0x38>;
243 pinctrl-0 = <&pinctrl_edt_ft5x06_1>;
253 reg = <0x48>;
255 pinctrl-0 = <&pinctrl_tsc2007>;
268 MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */
269 MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */
270 MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */
276 MX53_PAD_GPIO_9__KPP_COL_6 0x1f4
277 MX53_PAD_GPIO_4__KPP_COL_7 0x1f4
278 MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4
279 MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4
280 MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4
281 MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4
282 MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4
283 MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4
289 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
290 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
291 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
292 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
293 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
294 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
295 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
296 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
297 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
298 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
299 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
300 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
301 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
302 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
303 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
304 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
305 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
306 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
307 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
308 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
309 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
310 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
311 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
312 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
313 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
314 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
315 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
316 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
322 MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */
334 pinctrl-0 = <&pinctrl_kpp>;
336 /* row/col 0,1 are mapped to KPP row/col 6,7 */