Lines Matching +full:0 +full:x5
14 pinctrl-0 = <&pinctrl_rgb24>;
18 #size-cells = <0>;
20 port@0 {
21 reg = <0>;
42 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
43 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
44 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
45 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
46 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
47 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
48 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
49 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
50 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
51 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
52 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
53 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
54 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
55 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
56 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
57 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
58 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
59 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
60 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
61 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
62 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
63 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
64 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
65 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
66 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
67 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
68 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
69 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
75 MX53_PAD_SD1_DATA1__GPIO1_17 0x1f4
76 MX53_PAD_GPIO_7__GPIO1_7 0x1f4
77 MX53_PAD_PATA_DATA3__GPIO2_3 0x1f4
78 MX53_PAD_PATA_DATA8__GPIO2_8 0x1f4
100 pinctrl-0 = <&pinctrl_spi_gpio>;