Lines Matching +full:0 +full:x6001c600
20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0 0 0>;
36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
38 bus-range = <0x00 0xff>;
42 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
43 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
44 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
45 <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */
46 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
47 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
62 pci@1,0 {
64 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
65 reg = <0x000800 0 0 0 0>;
66 bus-range = <0x00 0xff>;
76 pci@2,0 {
78 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
79 reg = <0x001000 0 0 0 0>;
80 bus-range = <0x00 0xff>;
90 pci@3,0 {
92 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
93 reg = <0x001800 0 0 0 0>;
94 bus-range = <0x00 0xff>;
107 reg = <0x40000000 0x40000>;
110 ranges = <0 0x40000000 0x40000>;
113 reg = <0x400 0x3fc00>;
120 reg = <0x50000000 0x00024000>;
135 ranges = <0x54000000 0x54000000 0x04000000>;
139 reg = <0x54040000 0x00040000>;
154 reg = <0x54080000 0x00040000>;
169 reg = <0x540c0000 0x00040000>;
184 reg = <0x54100000 0x00040000>;
198 reg = <0x54140000 0x00040000>;
211 reg = <0x54180000 0x00040000>;
230 reg = <0x54200000 0x00040000>;
242 nvidia,head = <0>;
262 reg = <0x54240000 0x00040000>;
294 reg = <0x54280000 0x00040000>;
308 reg = <0x542c0000 0x00040000>;
318 reg = <0x54300000 0x00040000>;
331 reg = <0x54400000 0x00040000>;
345 reg = <0x50040600 0x20>;
354 reg = <0x50041000 0x1000>,
355 <0x50040100 0x0100>;
363 reg = <0x50043000 0x1000>;
372 reg = <0x60004000 0x100>,
373 <0x60004100 0x50>,
374 <0x60004200 0x50>,
375 <0x60004300 0x50>,
376 <0x60004400 0x50>;
384 reg = <0x60005000 0x400>;
385 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
396 reg = <0x60006000 0x1000>;
431 reg = <0x60007000 0x1000>;
436 reg = <0x6000a000 0x1400>;
477 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
482 reg = <0x6000c800 0x400>;
497 reg = <0x6000d000 0x1000>;
510 gpio-ranges = <&pinmux 0 0 248>;
515 reg = <0x6001a000 0x1000>, /* Syntax Engine */
516 <0x6001b000 0x1000>, /* Video Bitstream Engine */
517 <0x6001c000 0x100>, /* Macroblock Engine */
518 <0x6001c200 0x100>, /* Post-processing Engine */
519 <0x6001c400 0x100>, /* Motion Compensation Engine */
520 <0x6001c600 0x100>, /* Transform Engine */
521 <0x6001c800 0x100>, /* Pixel prediction block */
522 <0x6001ca00 0x100>, /* Video DMA */
523 <0x6001d800 0x400>; /* Video frame controls */
541 reg = <0x70000800 0x64>, /* Chip revision */
542 <0x70000008 0x04>; /* Strapping options */
547 reg = <0x70000868 0x0d4>, /* Pad control registers */
548 <0x70003000 0x3e4>; /* Mux registers */
561 reg = <0x70006000 0x40>;
573 reg = <0x70006040 0x40>;
585 reg = <0x70006200 0x100>;
597 reg = <0x70006300 0x100>;
609 reg = <0x70006400 0x100>;
621 reg = <0x70009000 0x1000>;
624 ranges = <0 0 0x48000000 0x7ffffff>;
636 reg = <0x7000a000 0x100>;
648 reg = <0x7000c000 0x100>;
651 #size-cells = <0>;
664 reg = <0x7000c400 0x100>;
667 #size-cells = <0>;
680 reg = <0x7000c500 0x100>;
683 #size-cells = <0>;
696 reg = <0x7000c700 0x100>;
699 #size-cells = <0>;
712 reg = <0x7000d000 0x100>;
715 #size-cells = <0>;
728 reg = <0x7000d400 0x200>;
731 #size-cells = <0>;
744 reg = <0x7000d600 0x200>;
747 #size-cells = <0>;
760 reg = <0x7000d800 0x200>;
763 #size-cells = <0>;
776 reg = <0x7000da00 0x200>;
779 #size-cells = <0>;
792 reg = <0x7000dc00 0x200>;
795 #size-cells = <0>;
808 reg = <0x7000de00 0x200>;
811 #size-cells = <0>;
824 reg = <0x7000e000 0x100>;
831 reg = <0x7000e200 0x100>;
841 reg = <0x7000e400 0x400>;
847 #power-domain-cells = <0>;
863 #power-domain-cells = <0>;
871 #power-domain-cells = <0>;
879 #power-domain-cells = <0>;
887 #power-domain-cells = <0>;
895 #power-domain-cells = <0>;
908 #power-domain-cells = <0>;
915 reg = <0x7000f000 0x400>;
928 reg = <0x7000f400 0x400>;
936 #interconnect-cells = <0>;
941 reg = <0x7000f800 0x400>;
952 reg = <0x70014000 0x500>;
966 reg = <0x70030000 0x10000>;
981 reg = <0x70080000 0x200>,
982 <0x70080200 0x100>;
1013 reg = <0x70080300 0x100>;
1023 reg = <0x70080400 0x100>;
1033 reg = <0x70080500 0x100>;
1043 reg = <0x70080600 0x100>;
1053 reg = <0x70080700 0x100>;
1064 reg = <0x78000000 0x200>;
1077 reg = <0x78000200 0x200>;
1088 reg = <0x78000400 0x200>;
1101 reg = <0x78000600 0x200>;
1112 reg = <0x7d000000 0x4000>;
1127 reg = <0x7d000000 0x4000>,
1128 <0x7d000000 0x4000>;
1137 #phy-cells = <0>;
1150 nvidia,pmc = <&tegra_pmc 0>;
1156 reg = <0x7d004000 0x4000>;
1170 reg = <0x7d004000 0x4000>,
1171 <0x7d000000 0x4000>;
1180 #phy-cells = <0>;
1198 reg = <0x7d008000 0x4000>;
1212 reg = <0x7d008000 0x4000>,
1213 <0x7d000000 0x4000>;
1222 #phy-cells = <0>;
1223 nvidia,hssync-start-delay = <0>;
1240 #size-cells = <0>;
1242 cpu0: cpu@0 {
1245 reg = <0>;
1289 thermal-sensors = <&tsensor 0>;
1330 polling-delay = <0>; /* milliseconds */