Lines Matching +full:0 +full:x70000800
21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
39 bus-range = <0x00 0xff>;
43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
46 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
47 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
60 pci@1,0 {
62 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
63 reg = <0x000800 0 0 0 0>;
64 bus-range = <0x00 0xff>;
74 pci@2,0 {
76 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
77 reg = <0x001000 0 0 0 0>;
78 bus-range = <0x00 0xff>;
91 reg = <0x0 0x50000000 0x0 0x00034000>;
104 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
108 reg = <0x0 0x54200000 0x0 0x00040000>;
117 nvidia,head = <0>;
135 reg = <0x0 0x54240000 0x0 0x00040000>;
158 reg = <0x0 0x54280000 0x0 0x00040000>;
170 reg = <0x0 0x54340000 0x0 0x00040000>;
182 reg = <0x0 0x54540000 0x0 0x00040000>;
197 reg = <0x0 0x545c0000 0x0 0x00040000>;
208 #size-cells = <0>;
217 reg = <0x0 0x50041000 0x0 0x1000>,
218 <0x0 0x50042000 0x0 0x1000>,
219 <0x0 0x50044000 0x0 0x2000>,
220 <0x0 0x50046000 0x0 0x2000>;
228 reg = <0x0 0x57000000 0x0 0x01000000>,
229 <0x0 0x58000000 0x0 0x01000000>;
246 reg = <0x0 0x60004000 0x0 0x100>,
247 <0x0 0x60004100 0x0 0x100>,
248 <0x0 0x60004200 0x0 0x100>,
249 <0x0 0x60004300 0x0 0x100>,
250 <0x0 0x60004400 0x0 0x100>;
258 reg = <0x0 0x60005000 0x0 0x400>;
259 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
270 reg = <0x0 0x60006000 0x0 0x1000>;
278 reg = <0x0 0x60007000 0x0 0x1000>;
283 reg = <0x0 0x6000c800 0x0 0x400>;
298 reg = <0x0 0x6000d000 0x0 0x1000>;
311 gpio-ranges = <&pinmux 0 0 251>;
316 reg = <0x0 0x60020000 0x0 0x1400>;
357 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
358 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
363 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
364 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
365 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
378 reg = <0x0 0x70006000 0x0 0x40>;
390 reg = <0x0 0x70006040 0x0 0x40>;
402 reg = <0x0 0x70006200 0x0 0x40>;
414 reg = <0x0 0x70006300 0x0 0x40>;
426 reg = <0x0 0x7000a000 0x0 0x100>;
436 reg = <0x0 0x7000c000 0x0 0x100>;
439 #size-cells = <0>;
451 reg = <0x0 0x7000c400 0x0 0x100>;
454 #size-cells = <0>;
466 reg = <0x0 0x7000c500 0x0 0x100>;
469 #size-cells = <0>;
481 reg = <0x0 0x7000c700 0x0 0x100>;
484 #size-cells = <0>;
496 reg = <0x0 0x7000d000 0x0 0x100>;
499 #size-cells = <0>;
511 reg = <0x0 0x7000d100 0x0 0x100>;
514 #size-cells = <0>;
526 reg = <0x0 0x7000d400 0x0 0x200>;
529 #size-cells = <0>;
541 reg = <0x0 0x7000d600 0x0 0x200>;
544 #size-cells = <0>;
556 reg = <0x0 0x7000d800 0x0 0x200>;
559 #size-cells = <0>;
571 reg = <0x0 0x7000da00 0x0 0x200>;
574 #size-cells = <0>;
586 reg = <0x0 0x7000dc00 0x0 0x200>;
589 #size-cells = <0>;
601 reg = <0x0 0x7000de00 0x0 0x200>;
604 #size-cells = <0>;
616 reg = <0x0 0x7000e000 0x0 0x100>;
623 reg = <0x0 0x7000e400 0x0 0x400>;
631 reg = <0x0 0x7000f800 0x0 0x400>;
640 reg = <0x0 0x70015000 0x0 0x00001000>;
650 reg = <0x0 0x70019000 0x0 0x1000>;
663 reg = <0x0 0x7001b000 0x0 0x1000>;
670 #interconnect-cells = <0>;
675 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
676 <0x0 0x70020000 0x0 0x7000>; /* SATA */
690 reg = <0x0 0x70030000 0x0 0x10000>;
705 reg = <0x0 0x70090000 0x0 0x8000>,
706 <0x0 0x70098000 0x0 0x1000>,
707 <0x0 0x70099000 0x0 0x1000>;
740 reg = <0x0 0x7009f000 0x0 0x1000>;
749 usb2-0 {
751 #phy-cells = <0>;
756 #phy-cells = <0>;
761 #phy-cells = <0>;
770 ulpi-0 {
772 #phy-cells = <0>;
781 hsic-0 {
783 #phy-cells = <0>;
788 #phy-cells = <0>;
797 pcie-0 {
799 #phy-cells = <0>;
804 #phy-cells = <0>;
809 #phy-cells = <0>;
814 #phy-cells = <0>;
819 #phy-cells = <0>;
828 sata-0 {
830 #phy-cells = <0>;
837 usb2-0 {
849 ulpi-0 {
853 hsic-0 {
861 usb3-0 {
873 reg = <0x0 0x700b0000 0x0 0x200>;
884 reg = <0x0 0x700b0200 0x0 0x200>;
895 reg = <0x0 0x700b0400 0x0 0x200>;
906 reg = <0x0 0x700b0600 0x0 0x200>;
917 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
918 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
943 reg = <0 0x70110000 0 0x100>, /* DFLL control */
944 <0 0x70110000 0 0x100>, /* I2C output control */
945 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
946 <0 0x70110200 0 0x100>; /* Look-up table RAM */
954 #clock-cells = <0>;
957 nvidia,droop-ctrl = <0x00000f00>;
960 nvidia,ci = <0>;
967 reg = <0x0 0x70300000 0x0 0x200>,
968 <0x0 0x70300800 0x0 0x800>,
969 <0x0 0x70300200 0x0 0x600>;
1019 reg = <0x0 0x70301000 0x0 0x100>;
1029 reg = <0x0 0x70301100 0x0 0x100>;
1039 reg = <0x0 0x70301200 0x0 0x100>;
1049 reg = <0x0 0x70301300 0x0 0x100>;
1059 reg = <0x0 0x70301400 0x0 0x100>;
1070 reg = <0x0 0x7d000000 0x0 0x4000>;
1082 reg = <0x0 0x7d000000 0x0 0x4000>,
1083 <0x0 0x7d000000 0x0 0x4000>;
1092 #phy-cells = <0>;
1093 nvidia,hssync-start-delay = <0>;
1098 nvidia,xcvr-lsfslew = <0>;
1104 nvidia,pmc = <&tegra_pmc 0>;
1110 reg = <0x0 0x7d004000 0x0 0x4000>;
1122 reg = <0x0 0x7d004000 0x0 0x4000>,
1123 <0x0 0x7d000000 0x0 0x4000>;
1132 #phy-cells = <0>;
1133 nvidia,hssync-start-delay = <0>;
1138 nvidia,xcvr-lsfslew = <0>;
1149 reg = <0x0 0x7d008000 0x0 0x4000>;
1161 reg = <0x0 0x7d008000 0x0 0x4000>,
1162 <0x0 0x7d000000 0x0 0x4000>;
1171 #phy-cells = <0>;
1172 nvidia,hssync-start-delay = <0>;
1177 nvidia,xcvr-lsfslew = <0>;
1188 #size-cells = <0>;
1190 cpu@0 {
1193 reg = <0>;
1230 interrupt-affinity = <&{/cpus/cpu@0}>,
1247 hysteresis = <0>;
1275 hysteresis = <0>;
1303 hysteresis = <0>;
1331 hysteresis = <0>;