Lines Matching +full:tegra20 +full:- +full:gr3d
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
24 #size-cells = <1>;
34 compatible = "nvidia,tegra114-host1x";
38 interrupt-names = "syncpt", "host1x";
40 clock-names = "host1x";
42 reset-names = "host1x", "mc";
45 #address-cells = <1>;
46 #size-cells = <1>;
51 compatible = "nvidia,tegra114-gr2d";
56 reset-names = "2d", "mc";
61 gr3d@54180000 {
62 compatible = "nvidia,tegra114-gr3d";
66 reset-names = "3d", "mc";
72 compatible = "nvidia,tegra114-dc";
77 clock-names = "dc", "parent";
79 reset-names = "dc";
91 compatible = "nvidia,tegra114-dc";
96 clock-names = "dc", "parent";
98 reset-names = "dc";
110 compatible = "nvidia,tegra114-hdmi";
115 clock-names = "hdmi", "parent";
117 reset-names = "hdmi";
122 compatible = "nvidia,tegra114-dsi";
127 clock-names = "dsi", "lp", "parent";
129 reset-names = "dsi";
130 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
133 #address-cells = <1>;
134 #size-cells = <0>;
138 compatible = "nvidia,tegra114-dsi";
143 clock-names = "dsi", "lp", "parent";
145 reset-names = "dsi";
146 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
149 #address-cells = <1>;
150 #size-cells = <0>;
154 gic: interrupt-controller@50041000 {
155 compatible = "arm,cortex-a15-gic";
156 #interrupt-cells = <3>;
157 interrupt-controller;
164 interrupt-parent = <&gic>;
167 lic: interrupt-controller@60004000 {
168 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
174 interrupt-controller;
175 #interrupt-cells = <3>;
176 interrupt-parent = <&gic>;
180 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer";
192 compatible = "nvidia,tegra114-car";
194 #clock-cells = <1>;
195 #reset-cells = <1>;
198 flow-controller@60007000 {
199 compatible = "nvidia,tegra114-flowctrl";
204 compatible = "nvidia,tegra114-apbdma";
240 reset-names = "dma";
241 #dma-cells = <1>;
245 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
250 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
260 #gpio-cells = <2>;
261 gpio-controller;
262 #interrupt-cells = <2>;
263 interrupt-controller;
264 gpio-ranges = <&pinmux 0 0 246>;
268 compatible = "nvidia,tegra114-vde";
272 <0x6001c200 0x100>, /* Post-processing Engine */
278 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
282 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
284 interrupt-names = "sync-token", "bsev", "sxe";
286 reset-names = "vde", "mc";
292 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
298 compatible = "nvidia,tegra114-pinmux";
307 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
309 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
312 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
314 reg-shift = <2>;
319 dma-names = "rx", "tx";
324 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
326 reg-shift = <2>;
331 dma-names = "rx", "tx";
336 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
338 reg-shift = <2>;
343 dma-names = "rx", "tx";
348 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
350 reg-shift = <2>;
355 dma-names = "rx", "tx";
360 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
362 #pwm-cells = <2>;
365 reset-names = "pwm";
370 compatible = "nvidia,tegra114-i2c";
373 #address-cells = <1>;
374 #size-cells = <0>;
376 clock-names = "div-clk";
378 reset-names = "i2c";
380 dma-names = "rx", "tx";
385 compatible = "nvidia,tegra114-i2c";
388 #address-cells = <1>;
389 #size-cells = <0>;
391 clock-names = "div-clk";
393 reset-names = "i2c";
395 dma-names = "rx", "tx";
400 compatible = "nvidia,tegra114-i2c";
403 #address-cells = <1>;
404 #size-cells = <0>;
406 clock-names = "div-clk";
408 reset-names = "i2c";
410 dma-names = "rx", "tx";
415 compatible = "nvidia,tegra114-i2c";
418 #address-cells = <1>;
419 #size-cells = <0>;
421 clock-names = "div-clk";
423 reset-names = "i2c";
425 dma-names = "rx", "tx";
430 compatible = "nvidia,tegra114-i2c";
433 #address-cells = <1>;
434 #size-cells = <0>;
436 clock-names = "div-clk";
438 reset-names = "i2c";
440 dma-names = "rx", "tx";
445 compatible = "nvidia,tegra114-spi";
448 #address-cells = <1>;
449 #size-cells = <0>;
451 clock-names = "spi";
453 reset-names = "spi";
455 dma-names = "rx", "tx";
460 compatible = "nvidia,tegra114-spi";
463 #address-cells = <1>;
464 #size-cells = <0>;
466 clock-names = "spi";
468 reset-names = "spi";
470 dma-names = "rx", "tx";
475 compatible = "nvidia,tegra114-spi";
478 #address-cells = <1>;
479 #size-cells = <0>;
481 clock-names = "spi";
483 reset-names = "spi";
485 dma-names = "rx", "tx";
490 compatible = "nvidia,tegra114-spi";
493 #address-cells = <1>;
494 #size-cells = <0>;
496 clock-names = "spi";
498 reset-names = "spi";
500 dma-names = "rx", "tx";
505 compatible = "nvidia,tegra114-spi";
508 #address-cells = <1>;
509 #size-cells = <0>;
511 clock-names = "spi";
513 reset-names = "spi";
515 dma-names = "rx", "tx";
520 compatible = "nvidia,tegra114-spi";
523 #address-cells = <1>;
524 #size-cells = <0>;
526 clock-names = "spi";
528 reset-names = "spi";
530 dma-names = "rx", "tx";
535 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
542 compatible = "nvidia,tegra114-kbc";
547 reset-names = "kbc";
552 compatible = "nvidia,tegra114-pmc";
555 clock-names = "pclk", "clk32k_in";
556 #clock-cells = <1>;
560 compatible = "nvidia,tegra114-efuse";
563 clock-names = "fuse";
565 reset-names = "fuse";
568 mc: memory-controller@70019000 {
569 compatible = "nvidia,tegra114-mc";
572 clock-names = "mc";
576 #reset-cells = <1>;
577 #iommu-cells = <1>;
581 compatible = "nvidia,tegra114-ahub";
588 clock-names = "d_audio", "apbif";
602 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
615 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
620 #address-cells = <1>;
621 #size-cells = <1>;
624 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
626 nvidia,ahub-cif-ids = <4 4>;
629 reset-names = "i2s";
634 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
636 nvidia,ahub-cif-ids = <5 5>;
639 reset-names = "i2s";
644 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
646 nvidia,ahub-cif-ids = <6 6>;
649 reset-names = "i2s";
654 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
656 nvidia,ahub-cif-ids = <7 7>;
659 reset-names = "i2s";
664 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
666 nvidia,ahub-cif-ids = <8 8>;
669 reset-names = "i2s";
675 compatible = "nvidia,tegra114-mipi";
678 #nvidia,mipi-calibrate-cells = <1>;
682 compatible = "nvidia,tegra114-sdhci";
686 clock-names = "sdhci";
688 reset-names = "sdhci";
693 compatible = "nvidia,tegra114-sdhci";
697 clock-names = "sdhci";
699 reset-names = "sdhci";
704 compatible = "nvidia,tegra114-sdhci";
708 clock-names = "sdhci";
710 reset-names = "sdhci";
715 compatible = "nvidia,tegra114-sdhci";
719 clock-names = "sdhci";
721 reset-names = "sdhci";
726 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
732 reset-names = "usb";
737 phy1: usb-phy@7d000000 {
738 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
746 clock-names = "reg", "pll_u", "utmi-pads";
748 reset-names = "usb", "utmi-pads";
749 #phy-cells = <0>;
750 nvidia,hssync-start-delay = <0>;
751 nvidia,idle-wait-delay = <17>;
752 nvidia,elastic-limit = <16>;
753 nvidia,term-range-adj = <6>;
754 nvidia,xcvr-setup = <9>;
755 nvidia,xcvr-lsfslew = <0>;
756 nvidia,xcvr-lsrslew = <3>;
757 nvidia,hssquelch-level = <2>;
758 nvidia,hsdiscon-level = <5>;
759 nvidia,xcvr-hsslew = <12>;
760 nvidia,has-utmi-pad-registers;
766 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
772 reset-names = "usb";
777 phy3: usb-phy@7d008000 {
778 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
786 clock-names = "reg", "pll_u", "utmi-pads";
788 reset-names = "usb", "utmi-pads";
789 #phy-cells = <0>;
790 nvidia,hssync-start-delay = <0>;
791 nvidia,idle-wait-delay = <17>;
792 nvidia,elastic-limit = <16>;
793 nvidia,term-range-adj = <6>;
794 nvidia,xcvr-setup = <9>;
795 nvidia,xcvr-lsfslew = <0>;
796 nvidia,xcvr-lsrslew = <3>;
797 nvidia,hssquelch-level = <2>;
798 nvidia,hsdiscon-level = <5>;
799 nvidia,xcvr-hsslew = <12>;
805 #address-cells = <1>;
806 #size-cells = <0>;
810 compatible = "arm,cortex-a15";
816 compatible = "arm,cortex-a15";
822 compatible = "arm,cortex-a15";
828 compatible = "arm,cortex-a15";
834 compatible = "arm,armv7-timer";
844 interrupt-parent = <&gic>;