Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
17 reg = <0x80000000 0x0>;
21 compatible = "mmio-sram";
22 reg = <0x40000000 0x40000>;
23 #address-cells = <1>;
24 #size-cells = <1>;
28 reg = <0x400 0x3fc00>;
34 compatible = "nvidia,tegra114-host1x";
35 reg = <0x50000000 0x00028000>;
38 interrupt-names = "syncpt", "host1x";
40 clock-names = "host1x";
42 reset-names = "host1x", "mc";
45 #address-cells = <1>;
46 #size-cells = <1>;
51 compatible = "nvidia,tegra114-gr2d";
52 reg = <0x54140000 0x00040000>;
56 reset-names = "2d", "mc";
62 compatible = "nvidia,tegra114-gr3d";
63 reg = <0x54180000 0x00040000>;
66 reset-names = "3d", "mc";
72 compatible = "nvidia,tegra114-dc";
73 reg = <0x54200000 0x00040000>;
77 clock-names = "dc", "parent";
79 reset-names = "dc";
91 compatible = "nvidia,tegra114-dc";
92 reg = <0x54240000 0x00040000>;
96 clock-names = "dc", "parent";
98 reset-names = "dc";
110 compatible = "nvidia,tegra114-hdmi";
111 reg = <0x54280000 0x00040000>;
115 clock-names = "hdmi", "parent";
117 reset-names = "hdmi";
122 compatible = "nvidia,tegra114-dsi";
123 reg = <0x54300000 0x00040000>;
127 clock-names = "dsi", "lp", "parent";
129 reset-names = "dsi";
130 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
133 #address-cells = <1>;
134 #size-cells = <0>;
138 compatible = "nvidia,tegra114-dsi";
139 reg = <0x54400000 0x00040000>;
143 clock-names = "dsi", "lp", "parent";
145 reset-names = "dsi";
146 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
149 #address-cells = <1>;
150 #size-cells = <0>;
154 gic: interrupt-controller@50041000 {
155 compatible = "arm,cortex-a15-gic";
156 #interrupt-cells = <3>;
157 interrupt-controller;
158 reg = <0x50041000 0x1000>,
164 interrupt-parent = <&gic>;
167 lic: interrupt-controller@60004000 {
168 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
169 reg = <0x60004000 0x100>,
174 interrupt-controller;
175 #interrupt-cells = <3>;
176 interrupt-parent = <&gic>;
180 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer";
181 reg = <0x60005000 0x400>;
192 compatible = "nvidia,tegra114-car";
193 reg = <0x60006000 0x1000>;
194 #clock-cells = <1>;
195 #reset-cells = <1>;
198 flow-controller@60007000 {
199 compatible = "nvidia,tegra114-flowctrl";
200 reg = <0x60007000 0x1000>;
204 compatible = "nvidia,tegra114-apbdma";
205 reg = <0x6000a000 0x1400>;
240 reset-names = "dma";
241 #dma-cells = <1>;
245 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
246 reg = <0x6000c000 0x150>;
250 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
251 reg = <0x6000d000 0x1000>;
260 #gpio-cells = <2>;
261 gpio-controller;
262 #interrupt-cells = <2>;
263 interrupt-controller;
264 gpio-ranges = <&pinmux 0 0 246>;
268 compatible = "nvidia,tegra114-vde";
269 reg = <0x6001a000 0x1000>, /* Syntax Engine */
272 <0x6001c200 0x100>, /* Post-processing Engine */
278 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
282 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
284 interrupt-names = "sync-token", "bsev", "sxe";
286 reset-names = "vde", "mc";
292 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
293 reg = <0x70000800 0x64>, /* Chip revision */
298 compatible = "nvidia,tegra114-pinmux";
299 reg = <0x70000868 0x148>, /* Pad control registers */
307 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
309 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
312 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
313 reg = <0x70006000 0x40>;
314 reg-shift = <2>;
319 dma-names = "rx", "tx";
324 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
325 reg = <0x70006040 0x40>;
326 reg-shift = <2>;
331 dma-names = "rx", "tx";
336 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
337 reg = <0x70006200 0x100>;
338 reg-shift = <2>;
343 dma-names = "rx", "tx";
348 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
349 reg = <0x70006300 0x100>;
350 reg-shift = <2>;
355 dma-names = "rx", "tx";
360 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
361 reg = <0x7000a000 0x100>;
362 #pwm-cells = <2>;
365 reset-names = "pwm";
370 compatible = "nvidia,tegra114-i2c";
371 reg = <0x7000c000 0x100>;
373 #address-cells = <1>;
374 #size-cells = <0>;
376 clock-names = "div-clk";
378 reset-names = "i2c";
380 dma-names = "rx", "tx";
385 compatible = "nvidia,tegra114-i2c";
386 reg = <0x7000c400 0x100>;
388 #address-cells = <1>;
389 #size-cells = <0>;
391 clock-names = "div-clk";
393 reset-names = "i2c";
395 dma-names = "rx", "tx";
400 compatible = "nvidia,tegra114-i2c";
401 reg = <0x7000c500 0x100>;
403 #address-cells = <1>;
404 #size-cells = <0>;
406 clock-names = "div-clk";
408 reset-names = "i2c";
410 dma-names = "rx", "tx";
415 compatible = "nvidia,tegra114-i2c";
416 reg = <0x7000c700 0x100>;
418 #address-cells = <1>;
419 #size-cells = <0>;
421 clock-names = "div-clk";
423 reset-names = "i2c";
425 dma-names = "rx", "tx";
430 compatible = "nvidia,tegra114-i2c";
431 reg = <0x7000d000 0x100>;
433 #address-cells = <1>;
434 #size-cells = <0>;
436 clock-names = "div-clk";
438 reset-names = "i2c";
440 dma-names = "rx", "tx";
445 compatible = "nvidia,tegra114-spi";
446 reg = <0x7000d400 0x200>;
448 #address-cells = <1>;
449 #size-cells = <0>;
451 clock-names = "spi";
453 reset-names = "spi";
455 dma-names = "rx", "tx";
460 compatible = "nvidia,tegra114-spi";
461 reg = <0x7000d600 0x200>;
463 #address-cells = <1>;
464 #size-cells = <0>;
466 clock-names = "spi";
468 reset-names = "spi";
470 dma-names = "rx", "tx";
475 compatible = "nvidia,tegra114-spi";
476 reg = <0x7000d800 0x200>;
478 #address-cells = <1>;
479 #size-cells = <0>;
481 clock-names = "spi";
483 reset-names = "spi";
485 dma-names = "rx", "tx";
490 compatible = "nvidia,tegra114-spi";
491 reg = <0x7000da00 0x200>;
493 #address-cells = <1>;
494 #size-cells = <0>;
496 clock-names = "spi";
498 reset-names = "spi";
500 dma-names = "rx", "tx";
505 compatible = "nvidia,tegra114-spi";
506 reg = <0x7000dc00 0x200>;
508 #address-cells = <1>;
509 #size-cells = <0>;
511 clock-names = "spi";
513 reset-names = "spi";
515 dma-names = "rx", "tx";
520 compatible = "nvidia,tegra114-spi";
521 reg = <0x7000de00 0x200>;
523 #address-cells = <1>;
524 #size-cells = <0>;
526 clock-names = "spi";
528 reset-names = "spi";
530 dma-names = "rx", "tx";
535 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
536 reg = <0x7000e000 0x100>;
542 compatible = "nvidia,tegra114-kbc";
543 reg = <0x7000e200 0x100>;
547 reset-names = "kbc";
552 compatible = "nvidia,tegra114-pmc";
553 reg = <0x7000e400 0x400>;
555 clock-names = "pclk", "clk32k_in";
556 #clock-cells = <1>;
560 compatible = "nvidia,tegra114-efuse";
561 reg = <0x7000f800 0x400>;
563 clock-names = "fuse";
565 reset-names = "fuse";
568 mc: memory-controller@70019000 {
569 compatible = "nvidia,tegra114-mc";
570 reg = <0x70019000 0x1000>;
572 clock-names = "mc";
576 #reset-cells = <1>;
577 #iommu-cells = <1>;
581 compatible = "nvidia,tegra114-hda", "nvidia,tegra30-hda";
582 reg = <0x70030000 0x10000>;
587 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
591 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
596 compatible = "nvidia,tegra114-ahub";
597 reg = <0x70080000 0x200>,
603 clock-names = "d_audio", "apbif";
617 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
630 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
635 #address-cells = <1>;
636 #size-cells = <1>;
639 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
640 reg = <0x70080300 0x100>;
641 nvidia,ahub-cif-ids = <4 4>;
644 reset-names = "i2s";
649 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
650 reg = <0x70080400 0x100>;
651 nvidia,ahub-cif-ids = <5 5>;
654 reset-names = "i2s";
659 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
660 reg = <0x70080500 0x100>;
661 nvidia,ahub-cif-ids = <6 6>;
664 reset-names = "i2s";
669 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
670 reg = <0x70080600 0x100>;
671 nvidia,ahub-cif-ids = <7 7>;
674 reset-names = "i2s";
679 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
680 reg = <0x70080700 0x100>;
681 nvidia,ahub-cif-ids = <8 8>;
684 reset-names = "i2s";
690 compatible = "nvidia,tegra114-mipi";
691 reg = <0x700e3000 0x100>;
693 #nvidia,mipi-calibrate-cells = <1>;
697 compatible = "nvidia,tegra114-sdhci";
698 reg = <0x78000000 0x200>;
701 clock-names = "sdhci";
703 reset-names = "sdhci";
708 compatible = "nvidia,tegra114-sdhci";
709 reg = <0x78000200 0x200>;
712 clock-names = "sdhci";
714 reset-names = "sdhci";
719 compatible = "nvidia,tegra114-sdhci";
720 reg = <0x78000400 0x200>;
723 clock-names = "sdhci";
725 reset-names = "sdhci";
730 compatible = "nvidia,tegra114-sdhci";
731 reg = <0x78000600 0x200>;
734 clock-names = "sdhci";
736 reset-names = "sdhci";
741 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
742 reg = <0x7d000000 0x4000>;
747 reset-names = "usb";
752 phy1: usb-phy@7d000000 {
753 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
754 reg = <0x7d000000 0x4000>,
761 clock-names = "reg", "pll_u", "utmi-pads";
763 reset-names = "usb", "utmi-pads";
764 #phy-cells = <0>;
765 nvidia,hssync-start-delay = <0>;
766 nvidia,idle-wait-delay = <17>;
767 nvidia,elastic-limit = <16>;
768 nvidia,term-range-adj = <6>;
769 nvidia,xcvr-setup = <9>;
770 nvidia,xcvr-lsfslew = <0>;
771 nvidia,xcvr-lsrslew = <3>;
772 nvidia,hssquelch-level = <2>;
773 nvidia,hsdiscon-level = <5>;
774 nvidia,xcvr-hsslew = <12>;
775 nvidia,has-utmi-pad-registers;
781 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
782 reg = <0x7d008000 0x4000>;
787 reset-names = "usb";
792 phy3: usb-phy@7d008000 {
793 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
794 reg = <0x7d008000 0x4000>,
801 clock-names = "reg", "pll_u", "utmi-pads";
803 reset-names = "usb", "utmi-pads";
804 #phy-cells = <0>;
805 nvidia,hssync-start-delay = <0>;
806 nvidia,idle-wait-delay = <17>;
807 nvidia,elastic-limit = <16>;
808 nvidia,term-range-adj = <6>;
809 nvidia,xcvr-setup = <9>;
810 nvidia,xcvr-lsfslew = <0>;
811 nvidia,xcvr-lsrslew = <3>;
812 nvidia,hssquelch-level = <2>;
813 nvidia,hsdiscon-level = <5>;
814 nvidia,xcvr-hsslew = <12>;
820 #address-cells = <1>;
821 #size-cells = <0>;
825 compatible = "arm,cortex-a15";
826 reg = <0>;
831 compatible = "arm,cortex-a15";
832 reg = <1>;
837 compatible = "arm,cortex-a15";
838 reg = <2>;
843 compatible = "arm,cortex-a15";
844 reg = <3>;
849 compatible = "arm,cortex-a15-pmu";
854 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
858 compatible = "arm,armv7-timer";
868 interrupt-parent = <&gic>;