Lines Matching +full:0 +full:xfc030000
47 #size-cells = <0>;
49 cpu@0 {
52 reg = <0>;
59 reg = <0x20000000 0x20000000>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
72 clock-frequency = <0>;
77 #clock-cells = <0>;
84 reg = <0x00210000 0x10000>;
87 ranges = <0 0x00210000 0x10000>;
99 reg = <0x100000 0x2400>;
102 ranges = <0 0x100000 0x2400>;
107 reg = <0x00300000 0x100000>;
114 reg = <0x00400000 0x100000
115 0xfc02c000 0x4000>;
124 reg = <0x00500000 0x100000>;
133 reg = <0x00600000 0x100000>;
142 reg = <0x00a00000 0x1000>;
153 reg = <0x10000000 0x10000000
154 0x60000000 0x28000000>;
155 ranges = <0x0 0x0 0x10000000 0x10000000
156 0x1 0x0 0x60000000 0x10000000
157 0x2 0x0 0x70000000 0x10000000
158 0x3 0x0 0x80000000 0x8000000>;
176 reg = <0x90000000 0x8000000>;
187 reg = <0xf0000000 0x4000>;
188 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
196 #size-cells = <0>;
198 port@0 {
200 #size-cells = <0>;
201 reg = <0>;
208 pinctrl-0 = <&pinctrl_lcd_pwm>;
215 reg = <0xf0004000 0x200>;
216 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
224 reg = <0xf0008000 0x4000>;
227 pinctrl-0 = <&pinctrl_isi_data_0_7>;
233 #size-cells = <0>;
239 reg = <0xf0010000 0x200>;
246 reg = <0xf0014000 0x200>;
247 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
255 reg = <0xf0018000 0x120>;
264 reg = <0xf8000000 0x600>;
265 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
267 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
268 | AT91_XDMAC_DT_PERID(0))>;
271 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
274 #size-cells = <0>;
281 reg = <0xf8004000 0x100>;
285 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
288 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
292 pinctrl-0 = <&pinctrl_uart0>;
300 reg = <0xf8008000 0x4000>;
301 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
303 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
305 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
308 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
318 reg = <0xf800c000 0x300>;
327 #size-cells = <0>;
329 reg = <0xf8010000 0x100>;
332 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
335 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
339 pinctrl-0 = <&pinctrl_spi0>;
347 reg = <0xf8014000 0x4000>;
350 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
353 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
357 pinctrl-0 = <&pinctrl_i2c0>;
362 #size-cells = <0>;
369 reg = <0xf8018000 0x4000>;
372 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
375 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
379 pinctrl-0 = <&pinctrl_i2c1>;
384 #size-cells = <0>;
392 #size-cells = <0>;
393 reg = <0xf801c000 0x100>;
394 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
401 reg = <0xf8020000 0x100>;
404 pinctrl-0 = <&pinctrl_macb0_rmii>;
406 #size-cells = <0>;
414 reg = <0xf8024000 0x4000>;
417 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
420 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
424 pinctrl-0 = <&pinctrl_i2c2>;
429 #size-cells = <0>;
436 reg = <0xf8028000 0x60>;
441 reg = <0xf802c000 0x100>;
445 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
448 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
452 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
460 reg = <0xf8030000 0x100>;
464 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
467 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
471 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
479 reg = <0xfc000000 0x600>;
480 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
482 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
486 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
489 #size-cells = <0>;
496 reg = <0xfc004000 0x100>;
500 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
503 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
507 pinctrl-0 = <&pinctrl_uart1>;
515 reg = <0xfc008000 0x100>;
519 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
522 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
526 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
534 reg = <0xfc00c000 0x100>;
538 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
541 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
545 pinctrl-0 = <&pinctrl_usart3>;
553 reg = <0xfc010000 0x100>;
557 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
560 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
564 pinctrl-0 = <&pinctrl_usart4>;
572 reg = <0xfc014000 0x4000>;
573 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
575 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
577 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
580 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
590 #size-cells = <0>;
592 reg = <0xfc018000 0x100>;
595 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
598 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
602 pinctrl-0 = <&pinctrl_spi1>;
610 #size-cells = <0>;
612 reg = <0xfc01c000 0x100>;
615 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
618 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
622 pinctrl-0 = <&pinctrl_spi2>;
631 #size-cells = <0>;
632 reg = <0xfc020000 0x100>;
633 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
641 #size-cells = <0>;
642 reg = <0xfc024000 0x100>;
643 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
650 reg = <0xfc028000 0x100>;
653 pinctrl-0 = <&pinctrl_macb1_rmii>;
655 #size-cells = <0>;
663 reg = <0xfc030000 0x100>;
664 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
670 reg = <0xfc034000 0x100>;
675 atmel,adc-channels-used = <0x01f>;
686 reg = <0xfc044000 0x100>;
687 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
688 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
690 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
699 reg = <0xfc04c000 0x100>;
700 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
701 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
703 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
712 reg = <0xfc050000 0x100>;
713 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
714 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
723 reg = <0xfc05c000 0x1000>;
732 reg = <0xfc05c070 0x490>,
733 <0xfc05c500 0x100>;
739 reg = <0xfc068600 0x10>;
745 reg = <0xfc068610 0x10>;
751 reg = <0xfc068630 0x10>;
758 reg = <0xfc068640 0x10>;
766 reg = <0xfc068650 0x4>;
767 #clock-cells = <0>;
773 reg = <0xfc0686b0 0x30>;
780 reg = <0xfc069000 0x200>;
784 pinctrl-0 = <&pinctrl_dbgu>;
795 ranges = <0xfc068000 0xfc068000 0x100
796 0xfc06a000 0xfc06a000 0x4000>;
800 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
801 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
802 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
803 0xb003ff00 0x8002a800 0x00000000 /* pioD */
804 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
809 reg = <0xfc06a000 0x100>;
820 reg = <0xfc06b000 0x100>;
831 reg = <0xfc06c000 0x100>;
842 reg = <0xfc068000 0x100>;
853 reg = <0xfc06d000 0x100>;
891 pinctrl_dbgu: dbgu-0 {
899 pinctrl_ebi_addr: ebi-addr-0 {
901 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE
935 pinctrl_ebi_cs0: ebi-cs0-0 {
940 pinctrl_ebi_cs1: ebi-cs1-0 {
945 pinctrl_ebi_cs2: ebi-cs2-0 {
950 pinctrl_ebi_cs3: ebi-cs3-0 {
955 pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
967 pinctrl_ebi_data_8_15: ebi-data-msb-0 {
979 pinctrl_ebi_nandrdy: ebi-nandrdy-0 {
984 pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 {
989 pinctrl_ebi_nwait: ebi-nwait-0 {
994 pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 {
999 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
1006 pinctrl_i2c0: i2c0-0 {
1020 pinctrl_i2c1: i2c1-0 {
1034 pinctrl_i2c2: i2c2-0 {
1048 pinctrl_isi_data_0_7: isi-0-data-0-7 {
1062 pinctrl_isi_data_8_9: isi-0-data-8-9 {
1064 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1067 pinctrl_isi_data_10_11: isi-0-data-10-11 {
1075 pinctrl_lcd_base: lcd-base-0 {
1082 pinctrl_lcd_pwm: lcd-pwm-0 {
1085 pinctrl_lcd_rgb444: lcd-rgb-0 {
1087 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1102 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1169 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1197 pinctrl_macb0_rmii: macb0_rmii-0 {
1206 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1214 pinctrl_macb1_rmii: macb1_rmii-0 {
1273 pinctrl_nand: nand-0 {
1283 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1295 pinctrl_spi0: spi0-0 {
1297 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1337 pinctrl_spi1: spi1-0 {
1347 pinctrl_spi2: spi2-0 {
1357 pinctrl_uart0: uart0-0 {
1366 pinctrl_uart1: uart1-0 {
1375 pinctrl_usart0: usart0-0 {
1381 pinctrl_usart0_rts: usart0_rts-0 {
1384 pinctrl_usart0_cts: usart0_cts-0 {
1390 pinctrl_usart1: usart1-0 {
1396 pinctrl_usart1_rts: usart1_rts-0 {
1399 pinctrl_usart1_cts: usart1_cts-0 {
1405 pinctrl_usart2: usart2-0 {
1411 pinctrl_usart2_rts: usart2_rts-0 {
1414 pinctrl_usart2_cts: usart2_cts-0 {
1420 pinctrl_usart3: usart3-0 {
1429 pinctrl_usart4: usart4-0 {
1435 pinctrl_usart4_rts: usart4_rts-0 {
1438 pinctrl_usart4_cts: usart4_cts-0 {
1439 … atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1448 reg = <0xfc06e000 0x200>;