Lines Matching +full:0 +full:xf0018000
46 #size-cells = <0>;
47 cpu@0 {
50 reg = <0x0>;
56 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
61 reg = <0x20000000 0x8000000>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
74 clock-frequency = <0>;
79 #clock-cells = <0>;
86 reg = <0x00300000 0x20000>;
89 ranges = <0 0x00300000 0x20000>;
106 reg = <0xf0000000 0x600>;
107 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
108 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
111 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
114 #size-cells = <0>;
121 #size-cells = <0>;
123 reg = <0xf0004000 0x100>;
129 pinctrl-0 = <&pinctrl_spi0>;
137 reg = <0xf0008000 0x4000>;
143 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
152 #size-cells = <0>;
153 reg = <0xf0010000 0x100>;
154 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
161 reg = <0xf0014000 0x4000>;
167 pinctrl-0 = <&pinctrl_i2c0>;
172 #size-cells = <0>;
179 reg = <0xf0018000 0x4000>;
185 pinctrl-0 = <&pinctrl_i2c1>;
190 #size-cells = <0>;
197 reg = <0xf001c000 0x100>;
204 pinctrl-0 = <&pinctrl_usart0>;
212 reg = <0xf0020000 0x100>;
219 pinctrl-0 = <&pinctrl_usart1>;
227 reg = <0xf0024000 0x100>;
231 pinctrl-0 = <&pinctrl_uart0>;
239 reg = <0xf002c000 0x300>;
248 reg = <0xf0034000 0x4000>;
251 pinctrl-0 = <&pinctrl_isi_data_0_7>;
257 #size-cells = <0>;
263 reg = <0xf0038000 0x60>;
268 reg = <0xf8000000 0x600>;
269 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
270 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
273 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
276 #size-cells = <0>;
283 #size-cells = <0>;
285 reg = <0xf8008000 0x100>;
291 pinctrl-0 = <&pinctrl_spi1>;
299 reg = <0xf800c000 0x4000>;
305 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
313 reg = <0xf8018000 0x100>;
316 pinctrl-0 = <
334 atmel,adc-channels-used = <0xfff>;
344 reg = <0xf801c000 0x4000>;
350 pinctrl-0 = <&pinctrl_i2c2>;
355 #size-cells = <0>;
362 reg = <0xf8020000 0x100>;
369 pinctrl-0 = <&pinctrl_usart2>;
377 reg = <0xf8024000 0x100>;
384 pinctrl-0 = <&pinctrl_usart3>;
392 reg = <0xf8034000 0x100>;
393 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
402 reg = <0xf8038000 0x100>;
403 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
413 reg = <0xf803c000 0x100>;
414 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
424 reg = <0xf8040000 0x100>;
425 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
431 reg = <0xffffc000 0x1000>;
440 reg = <0xffffc070 0x490>,
441 <0xffffc500 0x100>;
447 reg = <0xffffe600 0x200>;
448 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
456 reg = <0xffffe800 0x200>;
457 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
465 reg = <0xffffea00 0x200>;
472 reg = <0xffffee00 0x200>;
479 pinctrl-0 = <&pinctrl_dbgu>;
489 reg = <0xfffff000 0x200>;
497 ranges = <0xfffff200 0xfffff200 0xa00>;
500 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
501 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
502 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
503 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
504 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
564 pinctrl_dbgu: dbgu-0 {
572 pinctrl_ebi_addr: ebi-addr-0 {
605 pinctrl_ebi_cs0: ebi-cs0-0 {
610 pinctrl_ebi_cs1: ebi-cs1-0 {
615 pinctrl_ebi_cs2: ebi-cs2-0 {
620 pinctrl_ebi_nwait: ebi-nwait-0 {
625 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
632 pinctrl_i2c0: i2c0-0 {
646 pinctrl_i2c1: i2c1-0 {
660 pinctrl_i2c2: i2c2-0 {
674 pinctrl_isi_data_0_7: isi-0-data-0-7 {
689 pinctrl_isi_data_8_9: isi-0-data-8-9 {
695 pinctrl_isi_data_10_11: isi-0-data-10-11 {
706 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
740 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
748 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
754 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
756 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
765 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
777 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
790 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
798 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
807 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
815 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
826 pinctrl_spi0: spi0-0 {
835 pinctrl_spi1: spi1-0 {
876 pinctrl_uart0: uart0-0 {
884 pinctrl_uart1: uart1-0 {
892 pinctrl_usart0: usart0-0 {
898 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
906 pinctrl_usart1: usart1-0 {
912 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
920 pinctrl_usart2: usart2-0 {
926 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
934 pinctrl_usart3: usart3-0 {
940 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
950 reg = <0xfffff200 0x100>;
961 reg = <0xfffff400 0x100>;
972 reg = <0xfffff600 0x100>;
983 reg = <0xfffff800 0x100>;
994 reg = <0xfffffa00 0x100>;
1006 reg = <0xfffffc00 0x120>;
1015 reg = <0xfffffe00 0x10>;
1021 reg = <0xfffffe10 0x10>;
1027 reg = <0xfffffe30 0xf>;
1034 reg = <0xfffffe40 0x10>;
1045 reg = <0xfffffe50 0x4>;
1047 #clock-cells = <0>;
1052 reg = <0xfffffeb0 0x30>;
1061 reg = <0x200000 0x2400>;
1064 ranges = <0 0x200000 0x2400>;
1069 reg = <0x00500000 0x100000
1070 0xf8030000 0x4000>;
1079 reg = <0x00600000 0x100000>;
1088 reg = <0x00700000 0x100000>;
1100 reg = <0x10000000 0x10000000
1101 0x40000000 0x30000000>;
1102 ranges = <0x0 0x0 0x10000000 0x10000000
1103 0x1 0x0 0x40000000 0x10000000
1104 0x2 0x0 0x50000000 0x10000000
1105 0x3 0x0 0x60000000 0x10000000>;
1123 reg = <0x70000000 0x8000000>;