Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x03ffffff
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/pinctrl/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/clock/at91.h>
15 #include <dt-bindings/mfd/at91-usart.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
23 interrupt-parent = <&aic>;
36 #address-cells = <1>;
37 #size-cells = <0>;
39 cpu@0 {
40 compatible = "arm,arm926ej-s";
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
64 compatible = "mmio-sram";
65 reg = <0x00300000 0x100000>;
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges = <0 0x00300000 0x100000>;
72 compatible = "simple-bus";
73 #address-cells = <1>;
74 #size-cells = <1>;
78 #address-cells = <1>;
79 #size-cells = <0>;
80 compatible = "microchip,sam9x60-udc";
81 reg = <0x00500000 0x100000
82 0xf803c000 0x400>;
85 clock-names = "pclk", "hclk";
86 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
87 assigned-clock-rates = <480000000>;
92 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
93 reg = <0x00600000 0x100000>;
96 clock-names = "ohci_clk", "hclk", "uhpck";
101 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
102 reg = <0x00700000 0x100000>;
105 clock-names = "usb_clk", "ehci_clk";
106 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
107 assigned-clock-rates = <480000000>;
112 compatible = "microchip,sam9x60-ebi";
113 #address-cells = <2>;
114 #size-cells = <1>;
117 reg = <0x10000000 0x60000000>;
118 ranges = <0x0 0x0 0x10000000 0x10000000
119 0x1 0x0 0x20000000 0x10000000
120 0x2 0x0 0x30000000 0x10000000
121 0x3 0x0 0x40000000 0x10000000
122 0x4 0x0 0x50000000 0x10000000
123 0x5 0x0 0x60000000 0x10000000>;
127 nand_controller: nand-controller {
128 compatible = "microchip,sam9x60-nand-controller";
129 ecc-engine = <&pmecc>;
130 #address-cells = <2>;
131 #size-cells = <1>;
137 sdmmc0: sdio-host@80000000 {
138 compatible = "microchip,sam9x60-sdhci";
139 reg = <0x80000000 0x300>;
140 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
142 clock-names = "hclock", "multclk";
143 assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
144 assigned-clock-rates = <100000000>;
148 sdmmc1: sdio-host@90000000 {
149 compatible = "microchip,sam9x60-sdhci";
150 reg = <0x90000000 0x300>;
151 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
153 clock-names = "hclock", "multclk";
154 assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
155 assigned-clock-rates = <100000000>;
160 compatible = "simple-bus";
161 #address-cells = <1>;
162 #size-cells = <1>;
166 compatible = "atmel,sama5d2-flexcom";
167 reg = <0xf0000000 0x200>;
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0x0 0xf0000000 0x800>;
175 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
176 reg = <0x200 0x200>;
179 (AT91_XDMAC_DT_MEM_IF(0) |
183 (AT91_XDMAC_DT_MEM_IF(0) |
186 dma-names = "tx", "rx";
188 clock-names = "usart";
189 atmel,use-dma-rx;
190 atmel,use-dma-tx;
191 atmel,fifo-size = <16>;
196 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
197 reg = <0x400 0x200>;
200 clock-names = "spi_clk";
202 (AT91_XDMAC_DT_MEM_IF(0) |
206 (AT91_XDMAC_DT_MEM_IF(0) |
209 dma-names = "tx", "rx";
210 atmel,fifo-size = <16>;
215 compatible = "microchip,sam9x60-i2c";
216 reg = <0x600 0x200>;
218 #address-cells = <1>;
219 #size-cells = <0>;
222 (AT91_XDMAC_DT_MEM_IF(0) |
226 (AT91_XDMAC_DT_MEM_IF(0) |
229 dma-names = "tx", "rx";
230 atmel,fifo-size = <16>;
236 compatible = "atmel,sama5d2-flexcom";
237 reg = <0xf0004000 0x200>;
239 #address-cells = <1>;
240 #size-cells = <1>;
241 ranges = <0x0 0xf0004000 0x800>;
245 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
246 reg = <0x200 0x200>;
247 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
250 (AT91_XDMAC_DT_MEM_IF(0) |
254 (AT91_XDMAC_DT_MEM_IF(0) |
257 dma-names = "tx", "rx";
259 clock-names = "usart";
260 atmel,use-dma-rx;
261 atmel,use-dma-tx;
262 atmel,fifo-size = <16>;
267 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
268 reg = <0x400 0x200>;
271 clock-names = "spi_clk";
273 (AT91_XDMAC_DT_MEM_IF(0) |
277 (AT91_XDMAC_DT_MEM_IF(0) |
280 dma-names = "tx", "rx";
281 atmel,fifo-size = <16>;
286 compatible = "microchip,sam9x60-i2c";
287 reg = <0x600 0x200>;
289 #address-cells = <1>;
290 #size-cells = <0>;
293 (AT91_XDMAC_DT_MEM_IF(0) |
297 (AT91_XDMAC_DT_MEM_IF(0) |
300 dma-names = "tx", "rx";
301 atmel,fifo-size = <16>;
306 dma0: dma-controller@f0008000 {
307 compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
308 reg = <0xf0008000 0x1000>;
309 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
310 #dma-cells = <1>;
312 clock-names = "dma_clk";
316 compatible = "atmel,at91sam9g45-ssc";
317 reg = <0xf0010000 0x4000>;
320 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
323 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
325 dma-names = "tx", "rx";
327 clock-names = "pclk";
332 compatible = "microchip,sam9x60-qspi";
333 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
334 reg-names = "qspi_base", "qspi_mmap";
337 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
340 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
342 dma-names = "tx", "rx";
344 clock-names = "pclk", "qspick";
346 #address-cells = <1>;
347 #size-cells = <0>;
352 compatible = "microchip,sam9x60-i2smcc";
353 reg = <0xf001c000 0x100>;
356 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
359 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
361 dma-names = "tx", "rx";
363 clock-names = "pclk", "gclk";
368 compatible = "atmel,sama5d2-flexcom";
369 reg = <0xf0020000 0x200>;
371 #address-cells = <1>;
372 #size-cells = <1>;
373 ranges = <0x0 0xf0020000 0x800>;
377 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
378 reg = <0x200 0x200>;
381 (AT91_XDMAC_DT_MEM_IF(0) |
385 (AT91_XDMAC_DT_MEM_IF(0) |
388 dma-names = "tx", "rx";
390 clock-names = "usart";
391 atmel,use-dma-rx;
392 atmel,use-dma-tx;
393 atmel,fifo-size = <16>;
398 compatible = "microchip,sam9x60-i2c";
399 reg = <0x600 0x200>;
401 #address-cells = <1>;
402 #size-cells = <0>;
405 (AT91_XDMAC_DT_MEM_IF(0) |
409 (AT91_XDMAC_DT_MEM_IF(0) |
412 dma-names = "tx", "rx";
413 atmel,fifo-size = <16>;
419 compatible = "atmel,sama5d2-flexcom";
420 reg = <0xf0024000 0x200>;
422 #address-cells = <1>;
423 #size-cells = <1>;
424 ranges = <0x0 0xf0024000 0x800>;
428 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
429 reg = <0x200 0x200>;
432 (AT91_XDMAC_DT_MEM_IF(0) |
436 (AT91_XDMAC_DT_MEM_IF(0) |
439 dma-names = "tx", "rx";
441 clock-names = "usart";
442 atmel,use-dma-rx;
443 atmel,use-dma-tx;
444 atmel,fifo-size = <16>;
449 compatible = "microchip,sam9x60-i2c";
450 reg = <0x600 0x200>;
452 #address-cells = <1>;
453 #size-cells = <0>;
456 (AT91_XDMAC_DT_MEM_IF(0) |
460 (AT91_XDMAC_DT_MEM_IF(0) |
463 dma-names = "tx", "rx";
464 atmel,fifo-size = <16>;
470 compatible = "microchip,sam9x60-pit64b";
471 reg = <0xf0028000 0x100>;
474 clock-names = "pclk", "gclk";
478 compatible = "atmel,at91sam9g46-sha";
479 reg = <0xf002c000 0x100>;
480 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
482 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
484 dma-names = "tx";
486 clock-names = "sha_clk";
490 compatible = "microchip,sam9x60-trng";
491 reg = <0xf0030000 0x100>;
492 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
497 compatible = "atmel,at91sam9g46-aes";
498 reg = <0xf0034000 0x100>;
499 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
501 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
504 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
506 dma-names = "tx", "rx";
508 clock-names = "aes_clk";
512 compatible = "atmel,at91sam9g46-tdes";
513 reg = <0xf0038000 0x100>;
514 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
516 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
519 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
521 dma-names = "tx", "rx";
523 clock-names = "tdes_clk";
527 compatible = "atmel,sama5d2-classd";
528 reg = <0xf003c000 0x100>;
531 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
533 dma-names = "tx";
535 clock-names = "pclk", "gclk";
540 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
541 reg = <0xf8000000 0x300>;
544 clock-names = "can_clk";
549 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
550 reg = <0xf8004000 0x300>;
553 clock-names = "can_clk";
558 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
559 #address-cells = <1>;
560 #size-cells = <0>;
561 reg = <0xf8008000 0x100>;
562 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
563 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
564 clock-names = "t0_clk", "slow_clk";
568 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
569 #address-cells = <1>;
570 #size-cells = <0>;
571 reg = <0xf800c000 0x100>;
572 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
573 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
574 clock-names = "t0_clk", "slow_clk";
578 compatible = "atmel,sama5d2-flexcom";
579 reg = <0xf8010000 0x200>;
581 #address-cells = <1>;
582 #size-cells = <1>;
583 ranges = <0x0 0xf8010000 0x800>;
587 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
588 reg = <0x200 0x200>;
591 (AT91_XDMAC_DT_MEM_IF(0) |
595 (AT91_XDMAC_DT_MEM_IF(0) |
598 dma-names = "tx", "rx";
600 clock-names = "usart";
601 atmel,use-dma-rx;
602 atmel,use-dma-tx;
603 atmel,fifo-size = <16>;
608 compatible = "microchip,sam9x60-i2c";
609 reg = <0x600 0x200>;
611 #address-cells = <1>;
612 #size-cells = <0>;
615 (AT91_XDMAC_DT_MEM_IF(0) |
619 (AT91_XDMAC_DT_MEM_IF(0) |
622 dma-names = "tx", "rx";
623 atmel,fifo-size = <16>;
629 compatible = "atmel,sama5d2-flexcom";
630 reg = <0xf8014000 0x200>;
632 #address-cells = <1>;
633 #size-cells = <1>;
634 ranges = <0x0 0xf8014000 0x800>;
638 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
639 reg = <0x200 0x200>;
642 (AT91_XDMAC_DT_MEM_IF(0) |
646 (AT91_XDMAC_DT_MEM_IF(0) |
649 dma-names = "tx", "rx";
651 clock-names = "usart";
652 atmel,use-dma-rx;
653 atmel,use-dma-tx;
654 atmel,fifo-size = <16>;
659 compatible = "microchip,sam9x60-i2c";
660 reg = <0x600 0x200>;
662 #address-cells = <1>;
663 #size-cells = <0>;
666 (AT91_XDMAC_DT_MEM_IF(0) |
670 (AT91_XDMAC_DT_MEM_IF(0) |
673 dma-names = "tx", "rx";
674 atmel,fifo-size = <16>;
680 compatible = "atmel,sama5d2-flexcom";
681 reg = <0xf8018000 0x200>;
683 #address-cells = <1>;
684 #size-cells = <1>;
685 ranges = <0x0 0xf8018000 0x800>;
689 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
690 reg = <0x200 0x200>;
693 (AT91_XDMAC_DT_MEM_IF(0) |
697 (AT91_XDMAC_DT_MEM_IF(0) |
700 dma-names = "tx", "rx";
702 clock-names = "usart";
703 atmel,use-dma-rx;
704 atmel,use-dma-tx;
705 atmel,fifo-size = <16>;
710 compatible = "microchip,sam9x60-i2c";
711 reg = <0x600 0x200>;
713 #address-cells = <1>;
714 #size-cells = <0>;
717 (AT91_XDMAC_DT_MEM_IF(0) |
721 (AT91_XDMAC_DT_MEM_IF(0) |
724 dma-names = "tx", "rx";
725 atmel,fifo-size = <16>;
731 compatible = "atmel,sama5d2-flexcom";
732 reg = <0xf801c000 0x200>;
734 #address-cells = <1>;
735 #size-cells = <1>;
736 ranges = <0x0 0xf801c000 0x800>;
740 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
741 reg = <0x200 0x200>;
744 (AT91_XDMAC_DT_MEM_IF(0) |
746 AT91_XDMAC_DT_PERID(0))>,
748 (AT91_XDMAC_DT_MEM_IF(0) |
751 dma-names = "tx", "rx";
753 clock-names = "usart";
754 atmel,use-dma-rx;
755 atmel,use-dma-tx;
756 atmel,fifo-size = <16>;
761 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
762 reg = <0x400 0x200>;
765 clock-names = "spi_clk";
767 (AT91_XDMAC_DT_MEM_IF(0) |
769 AT91_XDMAC_DT_PERID(0))>,
771 (AT91_XDMAC_DT_MEM_IF(0) |
774 dma-names = "tx", "rx";
775 atmel,fifo-size = <16>;
780 compatible = "microchip,sam9x60-i2c";
781 reg = <0x600 0x200>;
783 #address-cells = <1>;
784 #size-cells = <0>;
787 (AT91_XDMAC_DT_MEM_IF(0) |
789 AT91_XDMAC_DT_PERID(0))>,
791 (AT91_XDMAC_DT_MEM_IF(0) |
794 dma-names = "tx", "rx";
795 atmel,fifo-size = <16>;
801 compatible = "atmel,sama5d2-flexcom";
802 reg = <0xf8020000 0x200>;
804 #address-cells = <1>;
805 #size-cells = <1>;
806 ranges = <0x0 0xf8020000 0x800>;
810 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
811 reg = <0x200 0x200>;
814 (AT91_XDMAC_DT_MEM_IF(0) |
818 (AT91_XDMAC_DT_MEM_IF(0) |
821 dma-names = "tx", "rx";
823 clock-names = "usart";
824 atmel,use-dma-rx;
825 atmel,use-dma-tx;
826 atmel,fifo-size = <16>;
831 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
832 reg = <0x400 0x200>;
835 clock-names = "spi_clk";
837 (AT91_XDMAC_DT_MEM_IF(0) |
841 (AT91_XDMAC_DT_MEM_IF(0) |
844 dma-names = "tx", "rx";
845 atmel,fifo-size = <16>;
850 compatible = "microchip,sam9x60-i2c";
851 reg = <0x600 0x200>;
853 #address-cells = <1>;
854 #size-cells = <0>;
857 (AT91_XDMAC_DT_MEM_IF(0) |
861 (AT91_XDMAC_DT_MEM_IF(0) |
864 dma-names = "tx", "rx";
865 atmel,fifo-size = <16>;
871 compatible = "atmel,sama5d2-flexcom";
872 reg = <0xf8024000 0x200>;
874 #address-cells = <1>;
875 #size-cells = <1>;
876 ranges = <0x0 0xf8024000 0x800>;
880 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
881 reg = <0x200 0x200>;
884 (AT91_XDMAC_DT_MEM_IF(0) |
888 (AT91_XDMAC_DT_MEM_IF(0) |
891 dma-names = "tx", "rx";
893 clock-names = "usart";
894 atmel,use-dma-rx;
895 atmel,use-dma-tx;
896 atmel,fifo-size = <16>;
901 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
902 reg = <0x400 0x200>;
905 clock-names = "spi_clk";
907 (AT91_XDMAC_DT_MEM_IF(0) |
911 (AT91_XDMAC_DT_MEM_IF(0) |
914 dma-names = "tx", "rx";
915 atmel,fifo-size = <16>;
920 compatible = "microchip,sam9x60-i2c";
921 reg = <0x600 0x200>;
923 #address-cells = <1>;
924 #size-cells = <0>;
927 (AT91_XDMAC_DT_MEM_IF(0) |
931 (AT91_XDMAC_DT_MEM_IF(0) |
934 dma-names = "tx", "rx";
935 atmel,fifo-size = <16>;
941 compatible = "atmel,sama5d2-flexcom";
942 reg = <0xf8028000 0x200>;
944 #address-cells = <1>;
945 #size-cells = <1>;
946 ranges = <0x0 0xf8028000 0x800>;
950 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
951 reg = <0x200 0x200>;
954 (AT91_XDMAC_DT_MEM_IF(0) |
958 (AT91_XDMAC_DT_MEM_IF(0) |
961 dma-names = "tx", "rx";
963 clock-names = "usart";
964 atmel,use-dma-rx;
965 atmel,use-dma-tx;
966 atmel,fifo-size = <16>;
971 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
972 reg = <0x400 0x200>;
975 clock-names = "spi_clk";
977 (AT91_XDMAC_DT_MEM_IF(0) |
981 (AT91_XDMAC_DT_MEM_IF(0) |
984 dma-names = "tx", "rx";
985 atmel,fifo-size = <16>;
990 compatible = "microchip,sam9x60-i2c";
991 reg = <0x600 0x200>;
993 #address-cells = <1>;
994 #size-cells = <0>;
997 (AT91_XDMAC_DT_MEM_IF(0) |
1001 (AT91_XDMAC_DT_MEM_IF(0) |
1004 dma-names = "tx", "rx";
1005 atmel,fifo-size = <16>;
1011 compatible = "cdns,sam9x60-macb", "cdns,macb";
1012 reg = <0xf802c000 0x1000>;
1015 clock-names = "hclk", "pclk";
1020 compatible = "cdns,sam9x60-macb", "cdns,macb";
1021 reg = <0xf8030000 0x1000>;
1024 clock-names = "hclk", "pclk";
1029 compatible = "microchip,sam9x60-pwm";
1030 reg = <0xf8034000 0x300>;
1033 #pwm-cells = <3>;
1038 compatible = "microchip,sam9x60-hlcdc";
1039 reg = <0xf8038000 0x4000>;
1040 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
1042 clock-names = "periph_clk","sys_clk", "slow_clk";
1043 assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
1044 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
1047 hlcdc-display-controller {
1048 compatible = "atmel,hlcdc-display-controller";
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1052 port@0 {
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1055 reg = <0>;
1059 hlcdc_pwm: hlcdc-pwm {
1060 compatible = "atmel,hlcdc-pwm";
1061 #pwm-cells = <3>;
1066 compatible = "atmel,sama5d2-flexcom";
1067 reg = <0xf8040000 0x200>;
1069 #address-cells = <1>;
1070 #size-cells = <1>;
1071 ranges = <0x0 0xf8040000 0x800>;
1075 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
1076 reg = <0x200 0x200>;
1079 (AT91_XDMAC_DT_MEM_IF(0) |
1083 (AT91_XDMAC_DT_MEM_IF(0) |
1086 dma-names = "tx", "rx";
1088 clock-names = "usart";
1089 atmel,use-dma-rx;
1090 atmel,use-dma-tx;
1091 atmel,fifo-size = <16>;
1096 compatible = "microchip,sam9x60-i2c";
1097 reg = <0x600 0x200>;
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1103 (AT91_XDMAC_DT_MEM_IF(0) |
1107 (AT91_XDMAC_DT_MEM_IF(0) |
1110 dma-names = "tx", "rx";
1111 atmel,fifo-size = <16>;
1117 compatible = "atmel,sama5d2-flexcom";
1118 reg = <0xf8044000 0x200>;
1120 #address-cells = <1>;
1121 #size-cells = <1>;
1122 ranges = <0x0 0xf8044000 0x800>;
1126 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
1127 reg = <0x200 0x200>;
1130 (AT91_XDMAC_DT_MEM_IF(0) |
1134 (AT91_XDMAC_DT_MEM_IF(0) |
1137 dma-names = "tx", "rx";
1139 clock-names = "usart";
1140 atmel,use-dma-rx;
1141 atmel,use-dma-tx;
1142 atmel,fifo-size = <16>;
1147 compatible = "microchip,sam9x60-i2c";
1148 reg = <0x600 0x200>;
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1154 (AT91_XDMAC_DT_MEM_IF(0) |
1158 (AT91_XDMAC_DT_MEM_IF(0) |
1161 dma-names = "tx", "rx";
1162 atmel,fifo-size = <16>;
1168 compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
1169 reg = <0xf8048000 0x100>;
1172 clock-names = "isi_clk";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1181 compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
1182 reg = <0xf804c000 0x100>;
1185 clock-names = "adc_clk";
1186 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
1187 dma-names = "rx";
1188 atmel,min-sample-rate-hz = <200000>;
1189 atmel,max-sample-rate-hz = <20000000>;
1190 atmel,startup-time-ms = <4>;
1191 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
1192 #io-channel-cells = <1>;
1197 compatible = "microchip,sam9x60-sfr", "syscon";
1198 reg = <0xf8050000 0x100>;
1202 compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
1203 reg = <0xffffde00 0x200>;
1206 pmecc: ecc-engine@ffffe000 {
1207 compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
1208 reg = <0xffffe000 0x300>,
1209 <0xffffe600 0x100>;
1213 compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
1214 reg = <0xffffe800 0x200>;
1216 clock-names = "ddrck", "mpddr";
1220 compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
1221 reg = <0xffffea00 0x100>;
1224 aic: interrupt-controller@fffff100 {
1225 compatible = "microchip,sam9x60-aic";
1226 #interrupt-cells = <3>;
1227 interrupt-controller;
1228 reg = <0xfffff100 0x100>;
1229 atmel,external-irqs = <31>;
1233 …compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel…
1234 reg = <0xfffff200 0x200>;
1235 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
1238 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1241 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1243 dma-names = "tx", "rx";
1245 clock-names = "usart";
1250 #address-cells = <1>;
1251 #size-cells = <1>;
1252 compatible = "microchip,sam9x60-pinctrl", "simple-mfd";
1253 ranges = <0xfffff400 0xfffff400 0x800>;
1255 /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
1256 atmel,mux-mask = <
1258 0xffffffff 0xffe03fff 0xef00019d /* pioA */
1259 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
1260 0xffffffff 0xffffffff 0xf83fffff /* pioC */
1261 0x003fffff 0x003f8000 0x00000000 /* pioD */
1265 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
1266 reg = <0xfffff400 0x200>;
1268 #gpio-cells = <2>;
1269 gpio-controller;
1270 interrupt-controller;
1271 #interrupt-cells = <2>;
1276 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
1277 reg = <0xfffff600 0x200>;
1279 #gpio-cells = <2>;
1280 gpio-controller;
1281 #gpio-lines = <26>;
1282 interrupt-controller;
1283 #interrupt-cells = <2>;
1288 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
1289 reg = <0xfffff800 0x200>;
1291 #gpio-cells = <2>;
1292 gpio-controller;
1293 interrupt-controller;
1294 #interrupt-cells = <2>;
1299 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
1300 reg = <0xfffffa00 0x200>;
1302 #gpio-cells = <2>;
1303 gpio-controller;
1304 #gpio-lines = <22>;
1305 interrupt-controller;
1306 #interrupt-cells = <2>;
1311 pmc: clock-controller@fffffc00 {
1312 compatible = "microchip,sam9x60-pmc", "syscon";
1313 reg = <0xfffffc00 0x200>;
1315 #clock-cells = <2>;
1316 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
1317 clock-names = "td_slck", "md_slck", "main_xtal";
1320 reset_controller: reset-controller@fffffe00 {
1321 compatible = "microchip,sam9x60-rstc";
1322 reg = <0xfffffe00 0x10>;
1323 clocks = <&clk32k 0>;
1327 compatible = "microchip,sam9x60-shdwc";
1328 reg = <0xfffffe10 0x10>;
1329 clocks = <&clk32k 0>;
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1332 atmel,wakeup-rtc-timer;
1333 atmel,wakeup-rtt-timer;
1338 compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
1339 reg = <0xfffffe20 0x20>;
1345 compatible = "atmel,at91sam9260-pit";
1346 reg = <0xfffffe40 0x10>;
1351 clk32k: clock-controller@fffffe50 {
1352 compatible = "microchip,sam9x60-sckc";
1353 reg = <0xfffffe50 0x4>;
1355 #clock-cells = <1>;
1359 compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
1360 reg = <0xfffffe60 0x10>;
1364 compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
1365 reg = <0xfffffea8 0x100>;
1371 compatible = "microchip,sam9x60-wdt";
1372 reg = <0xffffff80 0x24>;
1374 clocks = <&clk32k 0>;