Lines Matching +full:0 +full:xfffb0000
43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
54 reg = <0x20000000 0x04000000>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #clock-cells = <0>;
67 clock-frequency = <0>;
72 #clock-cells = <0>;
79 reg = <0x00300000 0x10000>;
82 ranges = <0 0x00300000 0x10000>;
93 reg = <0x00500000 0x1000>;
96 pinctrl-0 = <&pinctrl_fb>;
108 reg = <0x10000000 0x80000000>;
109 ranges = <0x0 0x0 0x10000000 0x10000000
110 0x1 0x0 0x20000000 0x10000000
111 0x2 0x0 0x30000000 0x10000000
112 0x3 0x0 0x40000000 0x10000000
113 0x4 0x0 0x50000000 0x10000000
114 0x5 0x0 0x60000000 0x10000000>;
136 #size-cells = <0>;
137 reg = <0xfffa0000 0x100>;
138 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
139 <17 IRQ_TYPE_LEVEL_HIGH 0>,
140 <18 IRQ_TYPE_LEVEL_HIGH 0>;
147 reg = <0xfffa4000 0x600>;
148 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
150 #size-cells = <0>;
159 reg = <0xfffa8000 0x100>;
162 #size-cells = <0>;
169 reg = <0xfffac000 0x100>;
172 #size-cells = <0>;
178 reg = <0xfffb0000 0x200>;
184 pinctrl-0 = <&pinctrl_usart0>;
192 reg = <0xfffb4000 0x200>;
198 pinctrl-0 = <&pinctrl_usart1>;
206 reg = <0xfffb8000 0x200>;
212 pinctrl-0 = <&pinctrl_usart2>;
220 reg = <0xfffbc000 0x200>;
226 pinctrl-0 = <&pinctrl_usart3>;
234 reg = <0xfffc0000 0x4000>;
237 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
243 reg = <0xfffc4000 0x4000>;
246 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
252 reg = <0xfffc8000 0x300>;
262 #size-cells = <0>;
264 reg = <0xfffcc000 0x200>;
267 pinctrl-0 = <&pinctrl_spi0>;
275 reg = <0xfffd0000 0x100>;
276 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
280 atmel,adc-channels-used = <0x3f>;
287 reg = <0x00600000 0x100000>,
288 <0xfffd4000 0x4000>;
297 reg = <0xffffe600 0x200>;
298 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
306 reg = <0xffffea00 0x200>;
311 reg = <0xffffec00 0x200>;
316 reg = <0xffffee00 0x200>;
323 reg = <0xfffff000 0x200>;
329 reg = <0xfffff200 0x200>;
333 pinctrl-0 = <&pinctrl_dbgu>;
343 ranges = <0xfffff400 0xfffff400 0x800>;
347 <0xffffffff 0xe05c6738>, /* pioA */
348 <0xffffffff 0x0000c780>, /* pioB */
349 <0xffffffff 0xe3ffff0e>, /* pioC */
350 <0x003fffff 0x0001ff3c>; /* pioD */
354 pinctrl_adc0_ts: adc0_ts-0 {
362 pinctrl_adc0_ad0: adc0_ad0-0 {
366 pinctrl_adc0_ad1: adc0_ad1-0 {
370 pinctrl_adc0_ad2: adc0_ad2-0 {
374 pinctrl_adc0_ad3: adc0_ad3-0 {
378 pinctrl_adc0_ad4: adc0_ad4-0 {
382 pinctrl_adc0_ad5: adc0_ad5-0 {
386 pinctrl_adc0_adtrg: adc0_adtrg-0 {
392 pinctrl_dbgu: dbgu-0 {
400 pinctrl_ebi_addr_nand: ebi-addr-0 {
408 pinctrl_fb: fb-0 {
435 pinctrl_i2c_gpio0: i2c_gpio0-0 {
443 pinctrl_i2c_gpio1: i2c_gpio1-0 {
451 pinctrl_mmc0_clk: mmc0_clk-0 {
456 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
458 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
462 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
471 pinctrl_nand_rb: nand-rb-0 {
476 pinctrl_nand_cs: nand-cs-0 {
481 pinctrl_nand_oe_we: nand-oe-we-0 {
489 pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
501 pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
513 pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
525 pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
535 pinctrl_spi0: spi0-0 {
544 pinctrl_ssc0_tx: ssc0_tx-0 {
547 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
551 pinctrl_ssc0_rx: ssc0_rx-0 {
560 pinctrl_ssc1_tx: ssc1_tx-0 {
567 pinctrl_ssc1_rx: ssc1_rx-0 {
576 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
580 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
584 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
588 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
592 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
596 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
600 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
604 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
608 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
614 pinctrl_usart0: usart0-0 {
620 pinctrl_usart0_rts: usart0_rts-0 {
625 pinctrl_usart0_cts: usart0_cts-0 {
630 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
636 pinctrl_usart0_dcd: usart0_dcd-0 {
641 pinctrl_usart0_ri: usart0_ri-0 {
646 pinctrl_usart0_sck: usart0_sck-0 {
653 pinctrl_usart1: usart1-0 {
659 pinctrl_usart1_rts: usart1_rts-0 {
664 pinctrl_usart1_cts: usart1_cts-0 {
669 pinctrl_usart1_sck: usart1_sck-0 {
676 pinctrl_usart2: usart2-0 {
682 pinctrl_usart2_rts: usart2_rts-0 {
687 pinctrl_usart2_cts: usart2_cts-0 {
692 pinctrl_usart2_sck: usart2_sck-0 {
699 pinctrl_usart3: usart3-0 {
701 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
705 pinctrl_usart3_rts: usart3_rts-0 {
710 pinctrl_usart3_cts: usart3_cts-0 {
715 pinctrl_usart3_sck: usart3_sck-0 {
723 reg = <0xfffff400 0x200>;
734 reg = <0xfffff600 0x200>;
745 reg = <0xfffff800 0x200>;
756 reg = <0xfffffa00 0x200>;
768 reg = <0xfffffc00 0x100>;
777 reg = <0xfffffd00 0x10>;
783 reg = <0xfffffd10 0x10>;
789 reg = <0xfffffd30 0xf>;
796 reg = <0xfffffd40 0x10>;
804 reg = <0xfffffd50 0x4>;
806 #clock-cells = <0>;
811 reg = <0xfffffd20 0x10>;
819 reg = <0xfffffd60 0x10>;
825 reg = <0xfffffe00 0x40>;
834 i2c-gpio-0 {
842 #size-cells = <0>;
844 pinctrl-0 = <&pinctrl_i2c_gpio0>;
856 #size-cells = <0>;
858 pinctrl-0 = <&pinctrl_i2c_gpio1>;