Lines Matching +full:mt6577 +full:- +full:timer
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/mt7629-clk.h>
11 #include <dt-bindings/power/mt7622-power.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/mt7629-resets.h>
18 interrupt-parent = <&sysirq>;
19 #address-cells = <1>;
20 #size-cells = <1>;
23 #address-cells = <1>;
24 #size-cells = <0>;
25 enable-method = "mediatek,mt6589-smp";
29 compatible = "arm,cortex-a7";
31 clock-frequency = <1250000000>;
32 cci-control-port = <&cci_control2>;
37 compatible = "arm,cortex-a7";
39 clock-frequency = <1250000000>;
40 cci-control-port = <&cci_control2>;
45 compatible = "arm,cortex-a7-pmu";
48 interrupt-affinity = <&cpu0>, <&cpu1>;
51 clk20m: oscillator-0 {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <20000000>;
55 clock-output-names = "clk20m";
58 clk40m: oscillator-1 {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <40000000>;
62 clock-output-names = "clkxtal";
65 timer {
66 compatible = "arm,armv7-timer";
67 interrupt-parent = <&gic>;
72 clock-frequency = <20000000>;
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
82 compatible = "mediatek,mt7629-infracfg", "syscon";
84 #clock-cells = <1>;
88 compatible = "mediatek,mt7629-pericfg", "syscon";
90 #clock-cells = <1>;
93 scpsys: power-controller@10006000 {
94 compatible = "mediatek,mt7629-scpsys",
95 "mediatek,mt7622-scpsys";
96 #power-domain-cells = <1>;
99 clock-names = "hif_sel";
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
105 timer: timer@10009000 { label
106 compatible = "mediatek,mt7629-timer",
107 "mediatek,mt6765-timer";
111 clock-names = "clk20m";
114 sysirq: interrupt-controller@10200a80 {
115 compatible = "mediatek,mt7629-sysirq",
116 "mediatek,mt6577-sysirq";
118 interrupt-controller;
119 #interrupt-cells = <3>;
120 interrupt-parent = <&gic>;
124 compatible = "mediatek,mt7629-apmixedsys", "syscon";
126 #clock-cells = <1>;
130 compatible = "mediatek,mt7629-rng",
131 "mediatek,mt7623-rng";
134 clock-names = "rng";
138 compatible = "mediatek,mt7629-topckgen", "syscon";
140 #clock-cells = <1>;
144 compatible = "mediatek,mt7629-wdt",
145 "mediatek,mt6589-wdt";
150 compatible = "mediatek,mt7629-pinctrl";
153 reg-names = "base", "eint";
154 gpio-controller;
155 gpio-ranges = <&pio 0 0 79>;
156 #gpio-cells = <2>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
160 interrupt-parent = <&gic>;
163 gic: interrupt-controller@10300000 {
164 compatible = "arm,gic-400";
165 interrupt-controller;
166 #interrupt-cells = <3>;
167 interrupt-parent = <&gic>;
175 compatible = "arm,cci-400";
176 #address-cells = <1>;
177 #size-cells = <1>;
181 cci_control0: slave-if@1000 {
182 compatible = "arm,cci-400-ctrl-if";
183 interface-type = "ace-lite";
187 cci_control1: slave-if@4000 {
188 compatible = "arm,cci-400-ctrl-if";
189 interface-type = "ace";
193 cci_control2: slave-if@5000 {
194 compatible = "arm,cci-400-ctrl-if";
195 interface-type = "ace";
200 compatible = "arm,cci-400-pmu,r1";
211 compatible = "mediatek,mt7629-uart",
212 "mediatek,mt6577-uart";
217 clock-names = "baud", "bus";
222 compatible = "mediatek,mt7629-uart",
223 "mediatek,mt6577-uart";
228 clock-names = "baud", "bus";
233 compatible = "mediatek,mt7629-uart",
234 "mediatek,mt6577-uart";
239 clock-names = "baud", "bus";
244 compatible = "mediatek,mt7629-pwm";
246 #pwm-cells = <2>;
250 clock-names = "top", "main", "pwm1";
251 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
252 assigned-clock-parents =
258 compatible = "mediatek,mt7629-i2c",
259 "mediatek,mt2712-i2c";
263 clock-div = <4>;
266 clock-names = "main", "dma";
267 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
268 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
269 #address-cells = <1>;
270 #size-cells = <0>;
275 compatible = "mediatek,mt7629-spi",
276 "mediatek,mt7622-spi";
277 #address-cells = <1>;
278 #size-cells = <0>;
284 clock-names = "parent-clk", "sel-clk", "spi-clk";
289 compatible = "mediatek,mt7629-nor",
290 "mediatek,mt8173-nor";
294 clock-names = "spi", "sf";
295 #address-cells = <1>;
296 #size-cells = <0>;
301 compatible = "mediatek,mt7629-ssusbsys", "syscon";
303 #clock-cells = <1>;
304 #reset-cells = <1>;
308 compatible = "mediatek,mt7629-xhci",
309 "mediatek,mtk-xhci";
312 reg-names = "mac", "ippc";
318 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
319 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
322 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
325 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
331 u3phy0: t-phy@1a0c4000 {
332 compatible = "mediatek,mt7629-tphy",
333 "mediatek,generic-tphy-v2";
334 #address-cells = <1>;
335 #size-cells = <1>;
339 u2port0: usb-phy@0 {
342 clock-names = "ref";
343 #phy-cells = <1>;
347 u3port0: usb-phy@700 {
350 clock-names = "ref";
351 #phy-cells = <1>;
357 compatible = "mediatek,mt7629-pciesys", "syscon";
359 #clock-cells = <1>;
360 #reset-cells = <1>;
364 compatible = "mediatek,generic-pciecfg", "syscon";
369 compatible = "mediatek,mt7629-pcie";
372 reg-names = "port1";
373 linux,pci-domain = <1>;
374 #address-cells = <3>;
375 #size-cells = <2>;
377 interrupt-names = "pcie_irq";
384 clock-names = "sys_ck1", "ahb_ck1",
387 assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>,
390 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
394 phy-names = "pcie-phy1";
395 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
396 bus-range = <0x00 0xff>;
400 #interrupt-cells = <1>;
401 interrupt-map-mask = <0 0 0 7>;
402 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
406 pcie_intc1: interrupt-controller {
407 interrupt-controller;
408 #address-cells = <0>;
409 #interrupt-cells = <1>;
413 pciephy1: t-phy@1a14a000 {
414 compatible = "mediatek,mt7629-tphy",
415 "mediatek,generic-tphy-v2";
416 #address-cells = <1>;
417 #size-cells = <1>;
421 pcieport1: pcie-phy@0 {
424 clock-names = "ref";
425 #phy-cells = <1>;
431 compatible = "mediatek,mt7629-ethsys", "syscon";
433 #clock-cells = <1>;
434 #reset-cells = <1>;
438 compatible = "mediatek,mt7629-eth","syscon";
460 clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1",
466 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
468 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
470 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
474 #address-cells = <1>;
475 #size-cells = <0>;
480 compatible = "mediatek,mt7629-sgmiisys", "syscon";
482 #clock-cells = <1>;
486 compatible = "mediatek,mt7629-sgmiisys", "syscon";
488 #clock-cells = <1>;