Lines Matching +full:mt6577 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/mt2701-clk.h>
13 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14 #include <dt-bindings/power/mt2701-power.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/reset/mt2701-resets.h>
18 #include <dt-bindings/thermal/thermal.h>
22 interrupt-parent = <&sysirq>;
23 #address-cells = <2>;
24 #size-cells = <2>;
26 cpu_opp_table: opp-table {
27 compatible = "operating-points-v2";
28 opp-shared;
30 opp-98000000 {
31 opp-hz = /bits/ 64 <98000000>;
32 opp-microvolt = <1050000>;
35 opp-198000000 {
36 opp-hz = /bits/ 64 <198000000>;
37 opp-microvolt = <1050000>;
40 opp-398000000 {
41 opp-hz = /bits/ 64 <398000000>;
42 opp-microvolt = <1050000>;
45 opp-598000000 {
46 opp-hz = /bits/ 64 <598000000>;
47 opp-microvolt = <1050000>;
50 opp-747500000 {
51 opp-hz = /bits/ 64 <747500000>;
52 opp-microvolt = <1050000>;
55 opp-1040000000 {
56 opp-hz = /bits/ 64 <1040000000>;
57 opp-microvolt = <1150000>;
60 opp-1196000000 {
61 opp-hz = /bits/ 64 <1196000000>;
62 opp-microvolt = <1200000>;
65 opp-1300000000 {
66 opp-hz = /bits/ 64 <1300000000>;
67 opp-microvolt = <1300000>;
72 #address-cells = <1>;
73 #size-cells = <0>;
74 enable-method = "mediatek,mt6589-smp";
78 compatible = "arm,cortex-a7";
82 clock-names = "cpu", "intermediate";
83 operating-points-v2 = <&cpu_opp_table>;
84 #cooling-cells = <2>;
85 clock-frequency = <1300000000>;
90 compatible = "arm,cortex-a7";
94 clock-names = "cpu", "intermediate";
95 operating-points-v2 = <&cpu_opp_table>;
96 #cooling-cells = <2>;
97 clock-frequency = <1300000000>;
102 compatible = "arm,cortex-a7";
106 clock-names = "cpu", "intermediate";
107 operating-points-v2 = <&cpu_opp_table>;
108 #cooling-cells = <2>;
109 clock-frequency = <1300000000>;
114 compatible = "arm,cortex-a7";
118 clock-names = "cpu", "intermediate";
119 operating-points-v2 = <&cpu_opp_table>;
120 #cooling-cells = <2>;
121 clock-frequency = <1300000000>;
126 compatible = "arm,cortex-a7-pmu";
131 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
135 compatible = "fixed-clock";
136 clock-frequency = <13000000>;
137 #clock-cells = <0>;
140 rtc32k: oscillator-1 {
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-frequency = <32000>;
144 clock-output-names = "rtc32k";
147 clk26m: oscillator-0 {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <26000000>;
151 clock-output-names = "clk26m";
154 thermal-zones {
155 cpu_thermal: cpu-thermal {
156 polling-delay-passive = <1000>;
157 polling-delay = <1000>;
159 thermal-sensors = <&thermal 0>;
162 cpu_passive: cpu-passive {
168 cpu_active: cpu-active {
174 cpu_hot: cpu-hot {
180 cpu-crit {
187 cooling-maps {
190 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
198 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
216 compatible = "arm,armv7-timer";
217 interrupt-parent = <&gic>;
222 clock-frequency = <13000000>;
223 arm,cpu-registers-not-fw-configured;
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
231 #clock-cells = <1>;
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
239 #clock-cells = <1>;
240 #reset-cells = <1>;
244 compatible = "mediatek,mt7623-pericfg",
245 "mediatek,mt2701-pericfg",
248 #clock-cells = <1>;
249 #reset-cells = <1>;
253 compatible = "mediatek,mt7623-pinctrl";
255 mediatek,pctl-regmap = <&syscfg_pctl_a>;
256 gpio-controller;
257 #gpio-cells = <2>;
258 interrupt-controller;
259 interrupt-parent = <&gic>;
260 #interrupt-cells = <2>;
266 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
270 scpsys: power-controller@10006000 {
271 compatible = "mediatek,mt7623-scpsys",
272 "mediatek,mt2701-scpsys",
274 #power-domain-cells = <1>;
280 clock-names = "mm", "mfg", "ethif";
284 compatible = "mediatek,mt7623-wdt",
285 "mediatek,mt6589-wdt";
290 compatible = "mediatek,mt7623-timer",
291 "mediatek,mt6577-timer";
295 clock-names = "system-clk", "rtc-clk";
299 compatible = "mediatek,mt7623-pwrap",
300 "mediatek,mt2701-pwrap";
302 reg-names = "pwrap";
305 reset-names = "pwrap";
308 clock-names = "spi", "wrap";
311 cir: ir-receiver@10013000 {
312 compatible = "mediatek,mt7623-cir";
316 clock-names = "clk";
320 sysirq: interrupt-controller@10200100 {
321 compatible = "mediatek,mt7623-sysirq",
322 "mediatek,mt6577-sysirq";
323 interrupt-controller;
324 #interrupt-cells = <3>;
325 interrupt-parent = <&gic>;
330 compatible = "mediatek,mt7623-efuse",
331 "mediatek,mt8173-efuse";
333 #address-cells = <1>;
334 #size-cells = <1>;
341 compatible = "mediatek,mt7623-apmixedsys",
342 "mediatek,mt2701-apmixedsys",
345 #clock-cells = <1>;
349 compatible = "mediatek,mt7623-rng";
352 clock-names = "rng";
355 gic: interrupt-controller@10211000 {
356 compatible = "arm,cortex-a7-gic";
357 interrupt-controller;
358 #interrupt-cells = <3>;
359 interrupt-parent = <&gic>;
367 compatible = "mediatek,mt7623-auxadc",
368 "mediatek,mt2701-auxadc";
371 clock-names = "main";
372 #io-channel-cells = <1>;
376 compatible = "mediatek,mt7623-uart",
377 "mediatek,mt6577-uart";
382 clock-names = "baud", "bus";
387 compatible = "mediatek,mt7623-uart",
388 "mediatek,mt6577-uart";
393 clock-names = "baud", "bus";
398 compatible = "mediatek,mt7623-uart",
399 "mediatek,mt6577-uart";
404 clock-names = "baud", "bus";
409 compatible = "mediatek,mt7623-uart",
410 "mediatek,mt6577-uart";
415 clock-names = "baud", "bus";
420 compatible = "mediatek,mt7623-pwm";
422 #pwm-cells = <2>;
430 clock-names = "top", "main", "pwm1", "pwm2",
435 i2c0: i2c@11007000 {
436 compatible = "mediatek,mt7623-i2c",
437 "mediatek,mt6577-i2c";
441 clock-div = <16>;
444 clock-names = "main", "dma";
445 #address-cells = <1>;
446 #size-cells = <0>;
450 i2c1: i2c@11008000 {
451 compatible = "mediatek,mt7623-i2c",
452 "mediatek,mt6577-i2c";
456 clock-div = <16>;
459 clock-names = "main", "dma";
460 #address-cells = <1>;
461 #size-cells = <0>;
465 i2c2: i2c@11009000 {
466 compatible = "mediatek,mt7623-i2c",
467 "mediatek,mt6577-i2c";
471 clock-div = <16>;
474 clock-names = "main", "dma";
475 #address-cells = <1>;
476 #size-cells = <0>;
481 compatible = "mediatek,mt7623-spi",
482 "mediatek,mt2701-spi";
483 #address-cells = <1>;
484 #size-cells = <0>;
490 clock-names = "parent-clk", "sel-clk", "spi-clk";
495 #thermal-sensor-cells = <1>;
496 compatible = "mediatek,mt7623-thermal",
497 "mediatek,mt2701-thermal";
501 clock-names = "therm", "auxadc";
503 reset-names = "therm";
506 nvmem-cells = <&thermal_calibration_data>;
507 nvmem-cell-names = "calibration-data";
511 compatible = "mediatek,mt7623-btif",
512 "mediatek,mtk-btif";
516 clock-names = "main";
517 reg-shift = <2>;
518 reg-io-width = <4>;
523 compatible = "mediatek,mt7623-nfc",
524 "mediatek,mt2701-nfc";
527 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
530 clock-names = "nfi_clk", "pad_clk";
532 ecc-engine = <&bch>;
533 #address-cells = <1>;
534 #size-cells = <0>;
538 compatible = "mediatek,mt7623-ecc",
539 "mediatek,mt2701-ecc";
543 clock-names = "nfiecc_clk";
548 compatible = "mediatek,mt7623-nor",
549 "mediatek,mt8173-nor";
553 clock-names = "spi", "sf";
554 #address-cells = <1>;
555 #size-cells = <0>;
560 compatible = "mediatek,mt7623-spi",
561 "mediatek,mt2701-spi";
562 #address-cells = <1>;
563 #size-cells = <0>;
569 clock-names = "parent-clk", "sel-clk", "spi-clk";
574 compatible = "mediatek,mt7623-spi",
575 "mediatek,mt2701-spi";
576 #address-cells = <1>;
577 #size-cells = <0>;
583 clock-names = "parent-clk", "sel-clk", "spi-clk";
588 compatible = "mediatek,mt7623-musb",
589 "mediatek,mtk-musb";
592 interrupt-names = "mc";
598 clock-names = "main","mcu","univpll";
599 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
603 u2phy1: t-phy@11210000 {
604 compatible = "mediatek,mt7623-tphy",
605 "mediatek,generic-tphy-v1";
607 #address-cells = <2>;
608 #size-cells = <2>;
612 u2port2: usb-phy@11210800 {
615 clock-names = "ref";
616 #phy-cells = <1>;
620 audsys: clock-controller@11220000 {
621 compatible = "mediatek,mt7623-audsys",
622 "mediatek,mt2701-audsys",
625 #clock-cells = <1>;
627 afe: audio-controller {
628 compatible = "mediatek,mt7623-audio",
629 "mediatek,mt2701-audio";
632 interrupt-names = "afe", "asys";
633 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
670 clock-names = "infra_sys_audio_clk",
705 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
709 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
711 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
716 compatible = "mediatek,mt7623-mmc",
717 "mediatek,mt2701-mmc";
722 clock-names = "source", "hclk";
727 compatible = "mediatek,mt7623-mmc",
728 "mediatek,mt2701-mmc";
733 clock-names = "source", "hclk";
738 compatible = "mediatek,mt7623-vdecsys",
739 "mediatek,mt2701-vdecsys",
742 #clock-cells = <1>;
746 compatible = "mediatek,mt7623-hifsys",
747 "mediatek,mt2701-hifsys";
749 #clock-cells = <1>;
750 #reset-cells = <1>;
754 compatible = "mediatek,mt7623-pcie";
760 reg-names = "subsys", "port0", "port1", "port2";
761 #address-cells = <3>;
762 #size-cells = <2>;
763 #interrupt-cells = <1>;
764 interrupt-map-mask = <0xf800 0 0 0>;
765 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
772 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
776 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
780 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
781 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
782 bus-range = <0x00 0xff>;
789 #address-cells = <3>;
790 #size-cells = <2>;
791 #interrupt-cells = <1>;
792 interrupt-map-mask = <0 0 0 0>;
793 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
800 #address-cells = <3>;
801 #size-cells = <2>;
802 #interrupt-cells = <1>;
803 interrupt-map-mask = <0 0 0 0>;
804 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
811 #address-cells = <3>;
812 #size-cells = <2>;
813 #interrupt-cells = <1>;
814 interrupt-map-mask = <0 0 0 0>;
815 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
821 pcie0_phy: t-phy@1a149000 {
822 compatible = "mediatek,mt7623-tphy",
823 "mediatek,generic-tphy-v1";
825 #address-cells = <2>;
826 #size-cells = <2>;
830 pcie0_port: pcie-phy@1a149900 {
833 clock-names = "ref";
834 #phy-cells = <1>;
839 pcie1_phy: t-phy@1a14a000 {
840 compatible = "mediatek,mt7623-tphy",
841 "mediatek,generic-tphy-v1";
843 #address-cells = <2>;
844 #size-cells = <2>;
848 pcie1_port: pcie-phy@1a14a900 {
851 clock-names = "ref";
852 #phy-cells = <1>;
858 compatible = "mediatek,mt7623-xhci",
859 "mediatek,mtk-xhci";
862 reg-names = "mac", "ippc";
866 clock-names = "sys_ck", "ref_ck";
867 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
872 u3phy1: t-phy@1a1c4000 {
873 compatible = "mediatek,mt7623-tphy",
874 "mediatek,generic-tphy-v1";
876 #address-cells = <2>;
877 #size-cells = <2>;
881 u2port0: usb-phy@1a1c4800 {
884 clock-names = "ref";
885 #phy-cells = <1>;
889 u3port0: usb-phy@1a1c4900 {
892 clock-names = "ref";
893 #phy-cells = <1>;
899 compatible = "mediatek,mt7623-xhci",
900 "mediatek,mtk-xhci";
903 reg-names = "mac", "ippc";
907 clock-names = "sys_ck", "ref_ck";
908 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
913 u3phy2: t-phy@1a244000 {
914 compatible = "mediatek,mt7623-tphy",
915 "mediatek,generic-tphy-v1";
917 #address-cells = <2>;
918 #size-cells = <2>;
922 u2port1: usb-phy@1a244800 {
925 clock-names = "ref";
926 #phy-cells = <1>;
930 u3port1: usb-phy@1a244900 {
933 clock-names = "ref";
934 #phy-cells = <1>;
940 compatible = "mediatek,mt7623-ethsys",
941 "mediatek,mt2701-ethsys",
944 #clock-cells = <1>;
945 #reset-cells = <1>;
948 hsdma: dma-controller@1b007000 {
949 compatible = "mediatek,mt7623-hsdma";
953 clock-names = "hsdma";
954 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
955 #dma-cells = <1>;
959 compatible = "mediatek,mt7623-eth",
960 "mediatek,mt2701-eth",
971 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
975 reset-names = "fe", "gmac", "ppe";
976 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
979 #address-cells = <1>;
980 #size-cells = <0>;
984 compatible = "mediatek,eth-mac";
990 compatible = "mediatek,eth-mac";
997 compatible = "mediatek,eip97-crypto";
1005 clock-names = "cryp";
1006 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1011 compatible = "mediatek,mt7623-bdpsys",
1012 "mediatek,mt2701-bdpsys",
1015 #clock-cells = <1>;
1020 cir_pins_a:cir-default {
1021 pins-cir {
1023 bias-disable;
1027 i2c0_pins_a: i2c0-default {
1028 pins-i2c0 {
1031 bias-disable;
1035 i2c1_pins_a: i2c1-default {
1036 pin-i2c1 {
1039 bias-disable;
1043 i2c1_pins_b: i2c1-alt {
1044 pin-i2c1 {
1047 bias-disable;
1051 i2c2_pins_a: i2c2-default {
1052 pin-i2c2 {
1055 bias-disable;
1059 i2c2_pins_b: i2c2-alt {
1060 pin-i2c2 {
1063 bias-disable;
1067 i2s0_pins_a: i2s0-default {
1068 pin-i2s0 {
1074 drive-strength = <MTK_DRIVE_12mA>;
1075 bias-pull-down;
1079 i2s1_pins_a: i2s1-default {
1080 pin-i2s1 {
1086 drive-strength = <MTK_DRIVE_12mA>;
1087 bias-pull-down;
1091 key_pins_a: keys-alt {
1092 pins-keys {
1095 input-enable;
1099 led_pins_a: leds-alt {
1100 pins-leds {
1108 pins-cmd-dat {
1118 input-enable;
1119 bias-pull-up;
1122 pins-clk {
1124 bias-pull-down;
1127 pins-rst {
1129 bias-pull-up;
1134 pins-cmd-dat {
1144 input-enable;
1145 drive-strength = <2>;
1146 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1149 pins-clk {
1151 drive-strength = <2>;
1152 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1155 pins-rst {
1157 bias-pull-up;
1162 pins-cmd-dat {
1168 input-enable;
1169 drive-strength = <4>;
1170 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1173 pins-clk {
1175 bias-pull-down;
1176 drive-strength = <4>;
1179 pins-wp {
1181 input-enable;
1182 bias-pull-up;
1185 pins-insert {
1187 bias-pull-up;
1192 pins-cmd-dat {
1198 input-enable;
1199 drive-strength = <4>;
1200 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1203 pins-clk {
1205 drive-strength = <4>;
1206 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1211 pins-ale {
1213 drive-strength = <8>;
1214 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1217 pins-dat {
1227 input-enable;
1228 drive-strength = <8>;
1229 bias-pull-up;
1232 pins-we {
1234 drive-strength = <8>;
1235 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1243 bias-disable;
1247 pwm_pins_a: pwm-default {
1248 pins-pwm {
1257 spi0_pins_a: spi0-default {
1258 pins-spi {
1263 bias-disable;
1267 spi1_pins_a: spi1-default {
1268 pins-spi {
1276 spi2_pins_a: spi2-default {
1277 pins-spi {
1285 uart0_pins_a: uart0-default {
1286 pins-dat {
1292 uart1_pins_a: uart1-default {
1293 pins-dat {
1299 uart2_pins_a: uart2-default {
1300 pins-dat {
1306 uart2_pins_b: uart2-alt {
1307 pins-dat {