Lines Matching +full:0 +full:x1100e000
73 #size-cells = <0>;
76 cpu0: cpu@0 {
79 reg = <0x0>;
91 reg = <0x1>;
103 reg = <0x2>;
115 reg = <0x3>;
137 #clock-cells = <0>;
142 #clock-cells = <0>;
147 clk26m: oscillator-0 {
149 #clock-cells = <0>;
159 thermal-sensors = <&thermal 0>;
230 reg = <0 0x10000000 0 0x1000>;
238 reg = <0 0x10001000 0 0x1000>;
247 reg = <0 0x10003000 0 0x1000>;
254 reg = <0 0x1000b000 0 0x1000>;
267 reg = <0 0x10005000 0 0x1000>;
275 reg = <0 0x10006000 0 0x1000>;
286 reg = <0 0x10007000 0 0x100>;
292 reg = <0 0x10008000 0 0x80>;
301 reg = <0 0x1000d000 0 0x1000>;
313 reg = <0 0x10013000 0 0x1000>;
326 reg = <0 0x10200100 0 0x1c>;
332 reg = <0 0x10206000 0 0x1000>;
336 reg = <0x424 0xc>;
344 reg = <0 0x10209000 0 0x1000>;
350 reg = <0 0x1020f000 0 0x1000>;
360 reg = <0 0x10211000 0 0x1000>,
361 <0 0x10212000 0 0x2000>,
362 <0 0x10214000 0 0x2000>,
363 <0 0x10216000 0 0x2000>;
369 reg = <0 0x11001000 0 0x1000>;
378 reg = <0 0x11002000 0 0x400>;
389 reg = <0 0x11003000 0 0x400>;
400 reg = <0 0x11004000 0 0x400>;
411 reg = <0 0x11005000 0 0x400>;
421 reg = <0 0x11006000 0 0x1000>;
438 reg = <0 0x11007000 0 0x70>,
439 <0 0x11000200 0 0x80>;
446 #size-cells = <0>;
453 reg = <0 0x11008000 0 0x70>,
454 <0 0x11000280 0 0x80>;
461 #size-cells = <0>;
468 reg = <0 0x11009000 0 0x70>,
469 <0 0x11000300 0 0x80>;
476 #size-cells = <0>;
484 #size-cells = <0>;
485 reg = <0 0x1100a000 0 0x100>;
498 reg = <0 0x1100b000 0 0x1000>;
499 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
513 reg = <0 0x1100c000 0 0x1000>;
525 reg = <0 0x1100d000 0 0x1000>;
534 #size-cells = <0>;
540 reg = <0 0x1100e000 0 0x1000>;
550 reg = <0 0x11014000 0 0x1000>;
555 #size-cells = <0>;
563 #size-cells = <0>;
564 reg = <0 0x11016000 0 0x100>;
577 #size-cells = <0>;
578 reg = <0 0x11017000 0 0x1000>;
590 reg = <0 0x11200000 0 0x1000>;
606 reg = <0 0x11210000 0 0x0800>;
613 reg = <0 0x11210800 0 0x0100>;
624 reg = <0 0x11220000 0 0x2000>;
711 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
718 reg = <0 0x11230000 0 0x1000>;
729 reg = <0 0x11240000 0 0x1000>;
741 reg = <0 0x16000000 0 0x1000>;
749 reg = <0 0x1a000000 0 0x1000>;
757 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
758 <0 0x1a142000 0 0x1000>, /* Port0 registers */
759 <0 0x1a143000 0 0x1000>, /* Port1 registers */
760 <0 0x1a144000 0 0x1000>; /* Port2 registers */
765 interrupt-map-mask = <0xf800 0 0 0>;
766 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
767 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
768 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
783 bus-range = <0x00 0xff>;
785 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
786 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
788 pcie@0,0 {
789 reg = <0x0000 0 0 0 0>;
793 interrupt-map-mask = <0 0 0 0>;
794 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
799 pcie@1,0 {
800 reg = <0x0800 0 0 0 0>;
804 interrupt-map-mask = <0 0 0 0>;
805 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
810 pcie@2,0 {
811 reg = <0x1000 0 0 0 0>;
815 interrupt-map-mask = <0 0 0 0>;
816 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
825 reg = <0 0x1a149000 0 0x0700>;
832 reg = <0 0x1a149900 0 0x0700>;
843 reg = <0 0x1a14a000 0 0x0700>;
850 reg = <0 0x1a14a900 0 0x0700>;
861 reg = <0 0x1a1c0000 0 0x1000>,
862 <0 0x1a1c4700 0 0x0100>;
876 reg = <0 0x1a1c4000 0 0x0700>;
883 reg = <0 0x1a1c4800 0 0x0100>;
891 reg = <0 0x1a1c4900 0 0x0700>;
902 reg = <0 0x1a240000 0 0x1000>,
903 <0 0x1a244700 0 0x0100>;
917 reg = <0 0x1a244000 0 0x0700>;
924 reg = <0 0x1a244800 0 0x0100>;
932 reg = <0 0x1a244900 0 0x0700>;
944 reg = <0 0x1b000000 0 0x1000>;
951 reg = <0 0x1b007000 0 0x1000>;
963 reg = <0 0x1b100000 0 0x20000>;
981 #size-cells = <0>;
984 gmac0: mac@0 {
986 reg = <0>;
999 reg = <0 0x1b240000 0 0x20000>;
1015 reg = <0 0x1c000000 0 0x1000>;