Lines Matching +full:mt2701 +full:- +full:cirq
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
19 #size-cells = <2>;
20 compatible = "mediatek,mt2701";
21 interrupt-parent = <&cirq>;
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "mediatek,mt81xx-tz-smp";
30 compatible = "arm,cortex-a7";
35 compatible = "arm,cortex-a7";
40 compatible = "arm,cortex-a7";
45 compatible = "arm,cortex-a7";
50 reserved-memory {
51 #address-cells = <2>;
52 #size-cells = <2>;
55 trustzone-bootinfo@80002000 {
56 compatible = "mediatek,trustzone-bootinfo";
62 compatible = "fixed-clock";
63 clock-frequency = <13000000>;
64 #clock-cells = <0>;
68 compatible = "fixed-clock";
69 clock-frequency = <32000>;
70 #clock-cells = <0>;
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <26000000>;
77 clock-output-names = "clk26m";
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <32000>;
84 clock-output-names = "rtc32k";
87 thermal-zones {
89 polling-delay-passive = <1000>; /* milliseconds */
90 polling-delay = <1000>; /* milliseconds */
92 thermal-sensors = <&thermal 0>;
93 sustainable-power = <1000>;
96 threshold: trip-point@0 {
102 target: trip-point@1 {
118 compatible = "arm,armv7-timer";
119 interrupt-parent = <&gic>;
127 compatible = "mediatek,mt2701-topckgen", "syscon";
129 #clock-cells = <1>;
133 compatible = "mediatek,mt2701-infracfg", "syscon";
135 #clock-cells = <1>;
136 #reset-cells = <1>;
140 compatible = "mediatek,mt2701-pericfg", "syscon";
142 #clock-cells = <1>;
143 #reset-cells = <1>;
147 compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
151 scpsys: power-controller@10006000 {
152 compatible = "mediatek,mt2701-scpsys", "syscon";
153 #power-domain-cells = <1>;
159 clock-names = "mm", "mfg", "ethif";
163 compatible = "mediatek,mt2701-wdt",
164 "mediatek,mt6589-wdt";
169 compatible = "mediatek,mt2701-timer",
170 "mediatek,mt6577-timer";
174 clock-names = "system-clk", "rtc-clk";
178 compatible = "mediatek,mt2701-pinctrl";
180 mediatek,pctl-regmap = <&syscfg_pctl_a>;
181 gpio-controller;
182 #gpio-cells = <2>;
183 interrupt-controller;
184 #interrupt-cells = <2>;
190 compatible = "mediatek,mt2701-smi-common";
195 clock-names = "apb", "smi", "async";
196 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
199 sysirq: interrupt-controller@10200100 {
200 compatible = "mediatek,mt2701-sysirq",
201 "mediatek,mt6577-sysirq";
202 interrupt-controller;
203 #interrupt-cells = <3>;
204 interrupt-parent = <&gic>;
208 cirq: interrupt-controller@10204000 { label
209 compatible = "mediatek,mt2701-cirq",
210 "mediatek,mtk-cirq";
211 interrupt-controller;
212 #interrupt-cells = <3>;
213 interrupt-parent = <&sysirq>;
215 mediatek,ext-irq-range = <32 200>;
219 compatible = "mediatek,mt2701-m4u";
223 clock-names = "bclk";
225 #iommu-cells = <1>;
229 compatible = "mediatek,mt2701-apmixedsys", "syscon";
231 #clock-cells = <1>;
234 gic: interrupt-controller@10211000 {
235 compatible = "arm,cortex-a7-gic";
236 interrupt-controller;
237 #interrupt-cells = <3>;
238 interrupt-parent = <&gic>;
246 compatible = "mediatek,mt2701-auxadc";
249 clock-names = "main";
250 #io-channel-cells = <1>;
255 compatible = "mediatek,mt2701-uart",
256 "mediatek,mt6577-uart";
260 clock-names = "baud", "bus";
265 compatible = "mediatek,mt2701-uart",
266 "mediatek,mt6577-uart";
270 clock-names = "baud", "bus";
275 compatible = "mediatek,mt2701-uart",
276 "mediatek,mt6577-uart";
280 clock-names = "baud", "bus";
285 compatible = "mediatek,mt2701-uart",
286 "mediatek,mt6577-uart";
290 clock-names = "baud", "bus";
295 compatible = "mediatek,mt2701-i2c",
296 "mediatek,mt6577-i2c";
300 clock-div = <16>;
302 clock-names = "main", "dma";
303 #address-cells = <1>;
304 #size-cells = <0>;
309 compatible = "mediatek,mt2701-i2c",
310 "mediatek,mt6577-i2c";
314 clock-div = <16>;
316 clock-names = "main", "dma";
317 #address-cells = <1>;
318 #size-cells = <0>;
323 compatible = "mediatek,mt2701-i2c",
324 "mediatek,mt6577-i2c";
328 clock-div = <16>;
330 clock-names = "main", "dma";
331 #address-cells = <1>;
332 #size-cells = <0>;
337 compatible = "mediatek,mt2701-spi";
338 #address-cells = <1>;
339 #size-cells = <0>;
345 clock-names = "parent-clk", "sel-clk", "spi-clk";
350 #thermal-sensor-cells = <0>;
351 compatible = "mediatek,mt2701-thermal";
355 clock-names = "therm", "auxadc";
357 reset-names = "therm";
362 nandc: nand-controller@1100d000 {
363 compatible = "mediatek,mt2701-nfc";
368 clock-names = "nfi_clk", "pad_clk";
370 ecc-engine = <&bch>;
371 #address-cells = <1>;
372 #size-cells = <0>;
376 compatible = "mediatek,mt2701-ecc";
380 clock-names = "nfiecc_clk";
385 compatible = "mediatek,mt2701-nor",
386 "mediatek,mt8173-nor";
390 clock-names = "spi", "sf";
391 #address-cells = <1>;
392 #size-cells = <0>;
397 compatible = "mediatek,mt2701-spi";
398 #address-cells = <1>;
399 #size-cells = <0>;
405 clock-names = "parent-clk", "sel-clk", "spi-clk";
410 compatible = "mediatek,mt2701-spi";
411 #address-cells = <1>;
412 #size-cells = <0>;
418 clock-names = "parent-clk", "sel-clk", "spi-clk";
422 audsys: clock-controller@11220000 {
423 compatible = "mediatek,mt2701-audsys", "syscon";
425 #clock-cells = <1>;
427 afe: audio-controller {
428 compatible = "mediatek,mt2701-audio";
431 interrupt-names = "afe", "asys";
432 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
469 clock-names = "infra_sys_audio_clk",
504 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
508 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
510 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
515 compatible = "mediatek,mt2701-mmsys", "syscon";
517 #clock-cells = <1>;
521 compatible = "mediatek,mt2701-disp-pwm";
523 #pwm-cells = <2>;
525 clock-names = "main", "mm";
530 compatible = "mediatek,mt2701-smi-larb";
533 mediatek,larb-id = <0>;
536 clock-names = "apb", "smi";
537 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
541 compatible = "mediatek,mt2701-imgsys", "syscon";
543 #clock-cells = <1>;
547 compatible = "mediatek,mt2701-smi-larb";
550 mediatek,larb-id = <2>;
553 clock-names = "apb", "smi";
554 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
558 compatible = "mediatek,mt2701-jpgdec";
563 clock-names = "jpgdec-smi",
565 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
571 compatible = "mediatek,mt2701-jpgenc",
572 "mediatek,mtk-jpgenc";
576 clock-names = "jpgenc";
577 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
583 compatible = "mediatek,mt2701-vdecsys", "syscon";
585 #clock-cells = <1>;
589 compatible = "mediatek,mt2701-smi-larb";
592 mediatek,larb-id = <1>;
595 clock-names = "apb", "smi";
596 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
600 compatible = "mediatek,mt2701-hifsys", "syscon";
602 #clock-cells = <1>;
603 #reset-cells = <1>;
607 compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
610 reg-names = "mac", "ippc";
614 clock-names = "sys_ck", "ref_ck";
615 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
620 u3phy0: t-phy@1a1c4000 {
621 compatible = "mediatek,mt2701-tphy",
622 "mediatek,generic-tphy-v1";
624 #address-cells = <2>;
625 #size-cells = <2>;
629 u2port0: usb-phy@1a1c4800 {
632 clock-names = "ref";
633 #phy-cells = <1>;
637 u3port0: usb-phy@1a1c4900 {
640 clock-names = "ref";
641 #phy-cells = <1>;
647 compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
650 reg-names = "mac", "ippc";
654 clock-names = "sys_ck", "ref_ck";
655 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
660 u3phy1: t-phy@1a244000 {
661 compatible = "mediatek,mt2701-tphy",
662 "mediatek,generic-tphy-v1";
664 #address-cells = <2>;
665 #size-cells = <2>;
669 u2port1: usb-phy@1a244800 {
672 clock-names = "ref";
673 #phy-cells = <1>;
677 u3port1: usb-phy@1a244900 {
680 clock-names = "ref";
681 #phy-cells = <1>;
687 compatible = "mediatek,mt2701-musb",
688 "mediatek,mtk-musb";
691 interrupt-names = "mc";
697 clock-names = "main","mcu","univpll";
698 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
702 u2phy0: t-phy@11210000 {
703 compatible = "mediatek,mt2701-tphy",
704 "mediatek,generic-tphy-v1";
706 #address-cells = <2>;
707 #size-cells = <2>;
711 u2port2: usb-phy@1a1c4800 {
714 clock-names = "ref";
715 #phy-cells = <1>;
721 compatible = "mediatek,mt2701-ethsys", "syscon";
723 #clock-cells = <1>;
724 #reset-cells = <1>;
728 compatible = "mediatek,mt2701-eth", "syscon";
738 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
742 reset-names = "fe", "gmac", "ppe";
743 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
746 #address-cells = <1>;
747 #size-cells = <0>;
752 compatible = "mediatek,mt2701-bdpsys", "syscon";
754 #clock-cells = <1>;